Method, control system and plant for processing a semiconductor wafer, and semiconductor wafer
Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.
1. A method of processing a semiconductor wafer, comprising minimally three processing operations: a first polishing operation in which the semiconductor wafer is subjected to double-sided polishing, followed by a second polishing operation in which the semiconductor wafer is subjected to chemical-mechanical polishing, followed by a coating operation in which the semiconductor wafer is subjected to epitaxial deposition of a layer,
the method comprising:
defining at least one operating parameter for each of the three processing operations, based, for each operating parameter definition, on at least one wafer parameter which is determined on the semiconductor wafer processed, on an actual state of a processing apparatus with which the respective processing operation is conducted, and on an optimization of wafer flatness parameters after undergoing all three processing operations, and not an optimization of the wafer flatness parameters after every individual processing step of the three processing operations, wherein one or more semiconductor wafers having an ESFQR max value at an edge exclusion of 2 mm, an edge division into 72 sectors and a sector length of 30 mm of not greater than 10 nm, an SFQR max value at an edge exclusion of 2 mm and a site area of 26 mm×8 mm of not greater than 10 nm, a ZDD av value at a radius position of 148 mm having a magnitude of not greater than 10 nm/mm 2 , and a GBIR value at an edge exclusion of 2 mm of not greater than 0.10 μm are obtained.
2. The method of claim 1 , wherein the wafer parameter determined is obtained from data from a flatness measurement.
3. The method of claim 1 , wherein at least one wafer parameter determined is ESFQD av .
4. The method of claim 1 , wherein the wafer flatness parameters are one or more of ESFQR max , SFQR max , ZDD av , and GBIR.
5. The method of claim 1 , wherein, for the first polishing operation, at least one corresponding operating parameter is established, selected from the group consisting of a polishing pressure, a polishing time, a speed of rotation of an upper polishing plate, a speed of rotation of a lower polishing plate, a speed of rotation of an inner drive ring, a speed of rotation of an outer drive ring, a temperature of the upper polishing plate, a temperature of the lower polishing plate, a composition of a polishing medium, a volume flow rate of the polishing medium, a temperature of the polishing medium, a pH of the polishing medium, a target differential of central thickness of the polished semiconductor wafer, and a mean thickness of a rotor disk used for polishing.
6. The method of claim 5 , wherein the at least one wafer parameter is determined by measurement on the particular semiconductor wafer or is determined using an evaluation based on the measurement of a multitude of semiconductor wafers processed.
7. The method of claim 1 , wherein, for the second polishing operation, at least one corresponding operating parameter is established, is selected from the group consisting of a radial distribution of a polishing pressure, a polishing time, a speed of rotation of a polishing plate, a speed of rotation of a carrier, a composition of a polishing medium, a volume flow rate of the polishing medium, a pH of the polishing medium, a temperature of the polishing plate, a temperature of the polishing medium, and a dressing of a polishing pad.
8. The method of claim 1 , wherein, for the coating operation, at least one corresponding operating parameter is established, selected from the group consisting of a volume flow rate of a deposition gas, a temperature of the deposition gas, a composition of the deposition gas, a duration of the deposition of the epitaxial layer, a speed of rotation of a susceptor, a distribution of heating output for heating of the semiconductor wafer, and additionally, if the coating operation prior to the deposition of the epitaxial layer comprises an etching operation, a volume flow rate of an etching gas, a temperature of the etching gas, a composition of the etching gas and a duration of the etching operation.
9. The method of claim 8 , wherein the etching gas is passed through the coating apparatus in the course of the etching operation.
10. The method of claim 1 , wherein, for at least one of the processing operations, at least one corresponding operating parameter is defined based on a target value of the at least one wafer parameter after undergoing at least one of the subsequent processing operations.
11. The method of claim 1 , wherein, for the second polishing operation, at least one operating parameter is defined such that, in a radial direction of the semiconductor wafer, regions are polished differently in the processing, via definition of different pressures onto different regions of the semiconductor wafer.
12. A control system for controlling processing apparatuses for processing a semiconductor wafer, comprising a first polishing apparatus in which the semiconductor wafer is subjected to double-sided polishing in a first polishing operation, a second polishing apparatus in which the semiconductor wafer is subjected to chemical-mechanical polishing in a second polishing operation, and a coating apparatus in which a layer is epitaxially deposited on the semiconductor wafer in a coating operation, wherein the control system conducts the method of claim 1 .
13. A plant for processing a semiconductor wafer, having minimally three processing apparatuses for processing operations, comprising a first polishing apparatus in which the semiconductor wafer can be subjected to double-sided polishing in a first polishing operation, a second polishing apparatus in which the semiconductor wafer can be subjected to chemical-mechanical polishing in a second polishing operation, and a coating apparatus in which a layer can be epitaxially deposited on the semiconductor wafers in a coating operation, and a control system of claim 12 .
14. A semiconductor wafer, having an ESFQR max value at an edge exclusion of 2 mm, an edge division into 72 sectors and a sector length of 30 mm of not greater than 10 nm, an SFQR max value at an edge exclusion of 2 mm and a site area of 26 mm×8 mm of not greater than 10 nm, a ZDD av value at a radius position of 148 mm having a magnitude of not greater than 10 nm/mm 2 , and a GBIR value at an edge exclusion of 2 mm of not greater than 0.10 μm.