Memory device architecture coupled to a System-on-Chip

1. An apparatus, comprising:

a System on Chip (SoC); and

a non-volatile memory device coupled to the SoC and having a structurally independent structure linked to the SoC, the non-volatile memory device comprising:

a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry;

sense amplifiers coupled to a corresponding sub array;

a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers, wherein each JTAG cell of the plurality of JTAG cells include:

a parallel input (PIN) terminal and a serial input (SIN) terminal; and

a parallel output terminal (POUT) and a serial output terminal (SOUT); and

a scan-chain connecting together the JTAG cells of the data buffer, wherein the scan-chain includes;

the PIN terminal of a first JTAG cell coupled to an output of a first sense amplifier;

the POUT terminal of the first JTAG cell is coupled to a corresponding data input/output terminal of the SoC;

the SIN terminal of the first JTAG cell is coupled to the SOUT terminal of a second JTAG cell; and

the SOUT terminal of the first JTAG cell is coupled to the SIN terminal of a third JTAG cell.

2. The apparatus of claim 1 , wherein each sub array is independently addressable inside the memory device.

3. The apparatus of claim 1 , wherein the scan-chain forms a single shift register for testing the interconnection between pads of the memory portion and corresponding pads of the SoC.

4. The apparatus of claim 1 , wherein the JTAG cells are serially connected in the scan-chain.

5. The apparatus of claim 1 , wherein the JTAG cells include a boundary scan cell comprising:

an input multiplexer

an output multiplexer; and

a pair of latches between the input multiplexer and the output multiplexer.

6. The apparatus of claim 5 , wherein the pair of latches are connected in a pipeline between a parallel input and a parallel output.

7. The apparatus of claim 1 , wherein a sub-array of the plurality of sub-arrays comprises super-pages including data, address, and ECC cells.

8. The apparatus of claim 1 , further comprising at least four sub arrays to communicate with corresponding cores of the SoC.

9. A non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device, comprising:

an array of memory cells formed by plurality of sub arrays;

sense amplifiers coupled to a corresponding sub array of the plurality of sub- arrays;

sense amplifiers coupled to the memory cells having respective outputs;

a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers, wherein each JTAG cell of the plurality of JTAG cells include;

a parallel input (PIN) terminal and a serial input (SIN) terminal; and

a parallel output terminal (POUT) and a serial output terminal (SOUT); and

a scan-chain connecting together the JTAG cells of the data buffer, wherein the scan-chain includes;

the PIN terminal of a first JTAG cell is coupled to an output of a first sense amplifier;

the POUT terminal of the first JTAG cell is coupled to a corresponding data input/output terminal of the SoC;

the SIN terminal of the first JTAG cell is coupled to SOUT terminal of a second JTAG cell; and

the SOUT terminal of the first JTAG cell is coupled to the SIN terminal of a third JTAG cell.

10. The non-volatile memory architecture of claim 9 , further comprising at least a pair of latches connected in a pipeline between a parallel input and a parallel output.

11. The non-volatile memory architecture of claim 9 , further comprising a channel of 168 pads for transmitting a super-page.

12. An integrated circuit, comprising:

a System on Chip (SoC) device; and

a non-volatile memory device coupled to the SoC, wherein the SoC and the non-volatile memory device are independent dies and are coupled via pins or pads, or both; and wherein:

a memory array in the memory device including a plurality of independently addressable sub arrays;

sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of the SoC device; and

a scan-chain comprising modified JTAG cells, wherein the scan-chain include a parallel input (PIN) terminal of a first JTAG cell coupled to an output of a first sense amplifier, a parallel output terminal (POUT) of the first JTAG cell coupled to a corresponding data input/output terminal of the SoC, a serial input (SIN) terminal of the first JTAG cell coupled to the serial output terminal (SOUT) of a second JTAG cell, and a serial output terminal (SOUT) of the first JTAG cell is coupled to a serial input (SIN) terminal of a third JTAG cell.

13. The integrated circuit of claim 12 , wherein, a sense amplifier is configured to provide an output combining data cells, address cells, and ECC cells.

14. The integrated circuit of claim 12 , wherein a sub-array of the plurality of independently addressable sub-arrays is organized in enlarged pages comprising data, address, and ECC bits.

15. The integrated circuit of claim 12 , wherein the modified JTAG cells are boundary-scan cells including a pair of latches between a parallel input and parallel output.

16. The integrated circuit of claim 12 , wherein the modified JTAG cells are serially connected in the scan-chain.

17. The integrated circuit of claim 12 , wherein each sub-array of a memory die of the memory device corresponds to a core of associated SoC device.

18. The integrated circuit of claim 12 , wherein the memory device is a Flash memory.

19. The integrated circuit of claim 12 , wherein the SoC device includes a plurality of cores each one in communication with a corresponding sub-array of the memory device a Direct Memory Access manner.

20. The integrated circuit of claim 12 , wherein an independent memory device includes logic circuitry with a Finite State Machine or RISC portion for communicating with the SoC device.