Half-bridge electronic device comprising two systems for minimizing dead-time between the switching operations of a high level switch and of a low level switch

1. An electronic half-bridge device, comprising:

a high level switch and a low level switch in series, connected at a midpoint, the low level switch and the high level switch being respectively controlled by a first activation/deactivation signal and a second activation/deactivation signal, the electronic half-bridge device being able to form, from an input signal, a first control signal of the same polarity as the input signal and offset by a dead time, and a second control signal of reversed polarity with respect to the input signal and offset b a dead time;

a first synchronization system including a first detection circuit configured to interpret a variation, along a falling edge, of a voltage (Vm) at the midpoint, the first synchronization system being configured to generate a first synchronization signal activated at a state 1 by the falling edge and reset to state 0 when the first control signal changes to state 1;

a second synchronization system including a second detection circuit configured to interpret a variation, along a rising edge, of the voltage (Vm) at the midpoint, the second synchronization system being configured to generate a second synchronization signal activated at a state 1 by the rising edge and reset to state 0 when the second control signal changes to state 1;

an OR logic gate combining the first synchronization signal with the first control signal, to form the first activation/deactivation signal; and

another OR logic gate combining the second synchronization signal with the second control signal, to form the second activation/deactivation signal.

2. The device of claim 1 , wherein each detection circuit comprises a capacitive element directly connected to the midpoint and configured to generate a transient current dependent on voltage variations at the midpoint.

3. The device of claim 2 , wherein each detection circuit comprises, in series with the capacitive element, a diode and a shunt resistor, for measuring a voltage proportional to the transient current.

4. The device of claim 3 , wherein each synchronization system includes a processing circuit configured to generate, from measurements of the detection circuit, the synchronization signal to activate the associated switch.

5. The device of claim 4 , wherein each processing circuit comprises a voltage comparator and a memory point.

6. The device of claim 5 , wherein at least one of the high- or low-level switches includes a high-voltage transistor.

7. The device of claim 6 , wherein the high-voltage transistor is formed on the basis of GaN.

8. The device of claim 7 , wherein at least one of the high- or low-level switches comprises a high voltage transistor in depletion mode in series with a low voltage transistor in enrichment mode.

9. A method for synchronizing an alternating activation of a low level switch and a high level switch in a half-bridge electronic device, comprising the following steps:

a) deactivating the low level switch when a first control signal changes to state 0, wherein the first control signal is formed from an input signal and is of the same polarity as said input signal and offset by a dead time;

b) interpreting a variation following a rising edge of a voltage at a midpoint, to generate a second synchronization signal capable of activating the high level switch, wherein the second synchronization signal is activated at a state 1 by the rising edge and reset to state 0 when a second control signal changes to state 1;

c) activating the high level switch, by a second activation/deactivation signal resulting from combining the second synchronization signal with the second control signal in an OR logic gate;

d) deactivating the high level switch when the second control signal changes to state 0, wherein the second control signal is formed from the input signal and is of reversed polarity with respect to said input signal and offset by a dead time;

e) interpreting a variation following a falling edge of the voltage at the midpoint to generate a first synchronization signal capable of activating the low level switch, wherein the first synchronization signal is activated at a state 1 by the falling edge and reset to state 0 when the first control signal changes to state 1; and

f) activating the low level switch, by a first activation/deactivation signal resulting from combining the first synchronization signal with the first control signal in another OR logic gate.

10. The method of claim 9 , further comprising repeating steps a) to f) for each new cycle of alternating switching of the low level switch and the high level switch.

11. The device of claim 1 , wherein each synchronization system includes a processing circuit configured to generate, from measurements of the detection circuit, the synchronization signal to activate the associated switch.

12. The device of claim 11 , wherein each processing circuit comprises a voltage comparator and a memory point.

13. The device of claim 1 , wherein at least one of the high- or low-level switches includes a high-voltage transistor.

14. The device of claim 13 , wherein the high-voltage transistor is formed on the basis of GaN.

15. The device of claim 13 , wherein at least one of the high- or low-level switches comprises the high-voltage transistor in depletion mode in series with a low-voltage transistor in enrichment mode.