IP Library Granted Patent US 11,417,733
Granted Patent B2
US 11,417,733 · App. 16/636,352 · Granted Aug 16, 2022

Semiconductor wafer of monocrystalline silicon and method of producing the semiconductor wafer

Inventors: Andreas Sattler (Trostberg, DE); Alexander Vollkopf (Burghausen, DE); Karl Mangelberger (Ach, AT)
Assignee: SILTRONIC AG
H01L29/32C30B15/206C30B25/20C30B29/06H01L21/02381H01L21/02428H01L21/02532H01L21/02579H01L21/02598H01L29/16
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Quick Facts
Patent No.
US 11,417,733
App. No.
16/636,352
Granted
Aug 16, 2022
Kind
B2
Abstract

Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p + -doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer; an oxygen concentration of the substrate wafer of not less than 5.3×10 17 atoms/cm 3 and not more than 6.0×10 17 atoms/cm 3 ; a resistivity of the substrate wafer of not less than 5 mΩcm and not more than 10 mΩcm; and the potential of the substrate wafer to form BMDs as a result of a heat treatment of the epitaxially coated semiconductor wafer, where a high density of BMDs has a maximum close to the surface of the substrate wafer.

Claims (9)

1. An epitaxially coated semiconductor wafer of monocrystalline silicon, comprising:

a p + -doped substrate wafer;

a p-doped epitaxial layer of monocrystalline silicon which covers an upper face of the substrate wafer;

an oxygen concentration of the substrate wafer of not less than 5.3×10 17 atoms/cm 3 and not more than 6.0×10 17 atoms/cm 3 ;

a resistivity of the substrate wafer of not less than 5 mΩcm and not more than 10 mΩcm; and

a potential of the substrate wafer to form BMDs (bulk microdefects) as a result of a two-stage heat treatment of the epitaxially coated semiconductor wafer, where the density of BMDs has a maximum of not less than 2×10 10 /cm 3 , the distance of the maximum from a front side of the epitaxially coated semiconductor wafer is not greater than 20 μm, and the ratio of the densities of BMDs at a distance of 20 μm and at a distance of 60 μm from the front side of the epitaxially coated semiconductor wafer is not less than 5, and the two-stage heat treatment is effected at 850° C. over a period of one hour in oxygen and at 1000° C. over a period of one hour in oxygen.

2. The epitaxially coated semiconductor wafer of claim 1 , wherein the epitaxial layer has a thickness of not less than 1 μm and not more than 5 μm.

3. The epitaxially coated semiconductor water of claim 1 , having a denuded zone having a thickness of not less than 3 μm and not more than 7 μm.

4. The epitaxially coated semiconductor wafer of claim 2 , having a denuded tone having a thickness of not less than 3 μm and not more than 7 μm.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: SATTLER, ANDREAS; VOLLKOPF, ALEXANDER; MANGELBERGER, KARL
To: SILTRONIC AG
Reel/Frame 051706/0754 →