Semiconductor device and method for manufacturing semiconductor device

1. A semiconductor device comprising:

a first insulator;

a first conductor and a second conductor over the first insulator;

a third conductor provided between the first conductor and the second conductor;

a dielectric covering the first insulator and the first to third conductors;

an oxide over the dielectric;

a second insulator positioned between the first conductor and the third conductor and in contact with the oxide;

a third insulator positioned between the second conductor and the third conductor and in contact with the oxide;

a fourth conductor in contact with the second insulator;

a fifth conductor in contact with the third insulator; and

a sixth conductor overlapping with the third conductor.

2. The semiconductor device according to claim 1 ,

wherein the oxide is in contact with a side surface and a bottom surface of the second insulator,

wherein the oxide is in contact with a side surface and a bottom surface of the third insulator,

wherein the second insulator is in contact with a side surface and a bottom surface of the fourth conductor, and

wherein the third insulator is in contact with a side surface and a bottom surface of the fifth conductor.

3. The semiconductor device according to claim 1 ,

wherein the oxide comprises In, an element M, and Zn, the element M being Al, Ga, Y, or Sn.

4. A semiconductor device comprising:

a first insulator;

a first conductor and a second conductor over the first insulator;

a third conductor provided between the first conductor and the second conductor;

a dielectric covering the first insulator and the first to third conductors;

an oxide over the dielectric;

a second insulator positioned between the first conductor and the third conductor and in contact with the oxide;

a third insulator positioned between the second conductor and the third conductor and in contact with the oxide;

a fourth conductor in contact with the second insulator;

a fifth conductor in contact with the third insulator; and

a sixth conductor overlapping with the third conductor,

wherein a first transistor comprises the oxide, the second insulator, and the fourth conductor,

wherein a second transistor comprises the oxide, the third insulator, and the fifth conductor,

wherein a first capacitor comprises the first conductor, the dielectric, and the oxide,

wherein a second capacitor comprises the second conductor, the dielectric, and the oxide,

wherein the first transistor and the second transistor are provided between the first capacitor and the second capacitor,

wherein one of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is also used as one electrode of the first capacitor,

wherein the other of the source and the drain of the second transistor is also used as one electrode of the second capacitor,

wherein a channel length of the first transistor is larger than a length in a direction parallel to a short side of the fourth conductor, and

wherein a channel length of the second transistor is larger than a length in a direction parallel to a short side of the fifth conductor.

5. The semiconductor device according to claim 4 , comprising:

a fourth insulator provided over the first transistor, the second transistor, the first capacitor, and the second capacitor;

an opening which is included in the fourth insulator and through which the oxide is exposed;

wherein the sixth conductor is provided in the opening; and

wherein a seventh conductor functioning as a wiring is provided over the fourth insulator and the sixth conductor.

6. The semiconductor device according to claim 5 ,

wherein the first to fifth conductors are provided to be substantially perpendicular to a direction of a long side of the oxide, and

wherein the seventh conductor is provided to be substantially parallel to the direction of the long side of the oxide.

7. A semiconductor device comprising:

a first insulator;

a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor over the first insulator;

a dielectric covering the first insulator and the first to fifth conductors;

an oxide over the dielectric;

a second insulator positioned between the first conductor and the second conductor and in contact with the oxide;

a third insulator positioned between the second conductor and the third conductor and in contact with the oxide;

a fourth insulator positioned between the third conductor and the fourth conductor and in contact with the oxide;

a fifth insulator positioned between the fourth conductor and the fifth conductor and in contact with the oxide;

a sixth conductor in contact with the second insulator;

a seventh conductor in contact with the third insulator;

an eighth conductor in contact with the fourth insulator;

a ninth conductor in contact with the fifth insulator;

a tenth conductor overlapping with the second conductor; and

an eleventh conductor overlapping with the fifth conductor;

wherein a first transistor comprises the oxide, the second insulator, and the sixth conductor,

wherein a second transistor comprises the oxide, the third insulator, and the seventh conductor,

wherein a third transistor comprises the oxide, the fourth insulator, and the eighth conductor,

wherein a fourth transistor comprises the oxide, the fifth insulator, and the ninth conductor,

wherein a first capacitor comprises the first conductor, the dielectric, and the oxide,

wherein a second capacitor comprises the third conductor, the dielectric, and the oxide,

wherein a third capacitor comprises the fourth conductor, the dielectric, and the oxide,

wherein the sixth conductor functions as a word line of a first memory circuit,

wherein the seventh conductor functions as a word line of a second memory circuit,

wherein the ninth conductor functions as a word line of a third memory circuit, and

wherein a voltage at which the third transistor is turned off is applied to the eighth conductor.

8. The semiconductor device according to claim 7 ,

wherein adjacent memory circuits are electrically isolated from each other by the voltage applied to the eighth conductor.

9. The semiconductor device according to claim 7 ,

wherein the tenth conductor and the eleventh conductor are electrically connected to a wiring functioning as a bit line of the first to third memory circuits.

10. The semiconductor device according to claim 7 ,

wherein the first to third capacitors function as capacitors of the first to third memory circuits, respectively.

11. A method for manufacturing a semiconductor device, comprising:

a step of forming a first conductor, a second conductor, and a third conductor in contact with a first insulator;

a step of forming a dielectric covering top surfaces and side surfaces of the first to third conductors;

a step of forming an oxide over the dielectric;

a step of forming a second insulator which is in contact with the oxide;

a step of forming a fourth conductor and a fifth conductor over the second insulator;

a step of forming a third insulator and a fourth insulator by etching the second insulator;

a step of increasing conductivity of a portion of the oxide that is over the first conductor; and

a step of forming a sixth conductor over the third conductor,

wherein the third insulator is between the first conductor and the third conductor,

wherein the fourth insulator is the second conductor and the third conductor,

wherein the fourth conductor overlaps with the third insulator, and

wherein the fifth conductor overlaps with the fourth insulator.