Display panel and display terminal
View Patent ↗A display panel and a display terminal are provided. The display panel includes a base substrate and a plurality of sub-pixels. The sub-pixels include a sub-pixel driving circuit and a light emitting device. The sub-pixel driving circuit includes a detection unit, a first light emitting control unit, and a second light emitting control unit. By detecting a potential of a second node, the light emitting device does not emit light abnormally, there is no need to perform dark line processing on the sub-pixels in a current row, and influence of dark lines is eliminated.
1. A display panel, comprising:
a base substrate, a plurality of sub-pixels arranged on the base substrate and arranged in an array, and a data signal line connected to the sub-pixels, wherein the sub-pixels comprise a sub-pixel driving circuit and a light emitting device, the sub-pixel driving circuit comprises a data signal input unit, a storage unit, a driving unit, a detection unit, a first light emitting control unit, and a second light emitting control unit;
wherein the data signal input unit is connected to a data signal and a first control signal, and is coupled to the driving unit at a first node;
wherein the driving unit is connected to a power high-voltage signal, and is coupled to the first light emitting control unit and the detection unit at a second node;
wherein the first light emitting control unit is connected to a first light emitting control signal, and is coupled to the light emitting device and the second light emitting control unit at a third node; and
wherein the second light emitting control unit is connected to a second light emitting control signal and is electrically connected to a node of a sub-pixel driving circuit of an adjacent row of the sub-pixels connected to a same data signal line.
2. The display panel according to claim 1 , wherein the first light emitting control unit comprises a first thin film transistor, a gate of the first thin film transistor is connected to the first light emitting control signal, a first end of the first thin film transistor is electrically connected to the second node, and a second end of the first thin film transistor is electrically connected to the third node.
3. The display panel according to claim 2 , wherein the second light emitting control unit comprises a second thin film transistor, a gate of the second thin film transistor is connected to a second light emitting control signal, a first end of the second thin film transistor is electrically connected to the third node, and a second end of the second thin film transistor is electrically connected to a node of a sub-pixel driving circuit of an adjacent row of the sub-pixels connected to a same data signal line.
4. The display panel according to claim 3 , wherein a potential of the first light emitting control signal and a potential of the second light emitting control signal are opposite.
5. The display panel according to claim 4 , wherein timing of the sub-pixel driving circuit comprises a reset phase, a threshold voltage storage phase, and a detection phase, the timing of the sub-pixel driving circuit further comprises a black insertion area, the black insertion area partially overlaps the threshold voltage storage phase, and the detection phase is located in the black insertion area.
6. The display panel according to claim 5 , wherein in the reset phase, the first control signal, the second driving signal, and the second light emitting control signal are all at a high potential, and the first light emitting control signal is at a low potential;
in the threshold voltage storage phase, the first control signal and the second light emitting control signal are both at the high potential, and the second control signal is at the low potential and changes to the high potential after entering the black insertion area; and
in the detection phase, the first control signal, the second control signal, and the second light emitting control signal are all at the high potential.
7. The display panel according to claim 6 , wherein the detection unit comprises a third thin film transistor, the display panel further comprises an external detection unit, a gate of the third thin film transistor is connected to the second control signal, a first end of the third thin film transistor is electrically connected to the second node, and a second end of the third thin film transistor is connected to the external detection unit.
8. The display panel according to claim 7 , wherein the external detection unit comprises a detection signal line, an initialization circuit, and a detection circuit, the detection signal line is coupled to the initialization circuit and the detection circuit at a fourth node, the initialization circuit is connected to an initialization control signal, and the detection circuit is connected to a scan signal.
9. The display panel according to claim 8 , wherein in the initialization phase, the initialization signal is at the high potential and the scan signal is at the low potential;
in the threshold voltage storage stage, the initialization signal is at the high potential and changes to the low potential after entering the black insertion area, and the scan signal is at the low potential; and
in the detection phase, the initialization signal is at the low potential, and the scan signal is changed from the low potential to the high potential.
10. A display terminal comprising a display panel, the display panel comprising:
a base substrate, a plurality of sub-pixels arranged on the base substrate and arranged in an array, and a data signal line connected to the sub-pixels, wherein the sub-pixels comprise a sub-pixel driving circuit and a light emitting device, the sub-pixel driving circuit comprises a data signal input unit, a storage unit, a driving unit, a detection unit, a first light emitting control unit, and a second light emitting control unit;
wherein the data signal input unit is connected to a data signal and a first control signal, and is coupled to the driving unit at a first node;
wherein the driving unit is connected to a power high-voltage signal, and is coupled to the first light emitting control unit and the detection unit at a second node;
wherein the first light emitting control unit is connected to a first light emitting control signal, and is coupled to the light emitting device and the second light emitting control unit at a third node; and
wherein the second light emitting control unit is connected to a second light emitting control signal and is electrically connected to a node of a sub-pixel driving circuit of an adjacent row of the sub-pixels connected to a same data signal line.
11. The display terminal according to claim 10 , wherein the first light emitting control unit comprises a first thin film transistor, a gate of the first thin film transistor is connected to the first light emitting control signal, a first end of the first thin film transistor is electrically connected to the second node, and a second end of the first thin film transistor is electrically connected to the third node.
12. The display terminal according to claim 11 , wherein the second light emitting control unit comprises a second thin film transistor, a gate of the second thin film transistor is connected to a second light emitting control signal, a first end of the second thin film transistor is electrically connected to the third node, and a second end of the second thin film transistor is electrically connected to a node of a sub-pixel driving circuit of an adjacent row of the sub-pixels connected to a same data signal line.
13. The display terminal according to claim 12 , wherein a potential of the first light emitting control signal and a potential of the second light emitting control signal are opposite.
14. The display terminal according to claim 13 , wherein timing of the sub-pixel driving circuit comprises a reset phase, a threshold voltage storage phase, and a detection phase, the timing of the sub-pixel driving circuit further comprises a black insertion area, the black insertion area partially overlaps the threshold voltage storage phase, and the detection phase is located in the black insertion area.
15. The display terminal according to claim 14 , wherein in the reset phase, the first control signal, the second driving signal, and the second light emitting control signal are all at a high potential, and the first light emitting control signal is at a low potential;
in the threshold voltage storage phase, the first control signal and the second light emitting control signal are both at the high potential, and the second control signal is at the low potential and changes to the high potential after entering the black insertion area; and
in the detection phase, the first control signal, the second control signal, and the second light emitting control signal are all at the high potential.
16. The display terminal according to claim 15 , wherein the detection unit comprises a third thin film transistor, the display panel further comprises an external detection unit, a gate of the third thin film transistor is connected to the second control signal, a first end of the third thin film transistor is electrically connected to the second node, and a second end of the third thin film transistor is connected to the external detection unit.
17. The display terminal according to claim 16 , wherein the external detection unit comprises a detection signal line, an initialization circuit, and a detection circuit, the detection signal line is coupled to the initialization circuit and the detection circuit at a fourth node, the initialization circuit is connected to an initialization control signal, and the detection circuit is connected to a scan signal.
18. The display terminal according to claim 17 , wherein in the initialization phase, the initialization signal is at the high potential and the scan signal is at the low potential;
in the threshold voltage storage stage, the initialization signal is at the high potential and changes to the low potential after entering the black insertion area, and the scan signal is at the low potential; and
in the detection phase, the initialization signal is at the low potential, and the scan signal is changed from the low potential to the high potential.
19. A display terminal comprising a display panel, the display panel comprising:
a base substrate, a plurality of sub-pixels arranged on the base substrate and arranged in an array, and a data signal line connected to the sub-pixels, wherein the sub-pixels comprise a sub-pixel driving circuit and a light emitting device, the sub-pixel driving circuit comprises a data signal input unit, a storage unit, a driving unit, a detection unit, a first light emitting control unit, and a second light emitting control unit;
wherein the data signal input unit is connected to a data signal and a first control signal, and is coupled to the driving unit at a first node;
wherein the driving unit is connected to a power high-voltage signal, and is coupled to the first light emitting control unit and the detection unit at a second node;
wherein the first light emitting control unit comprises a first thin film transistor, a gate of the first thin film transistor is connected to the first light emitting control signal, a first end of the first thin film transistor is electrically connected to the second node; and
wherein the second light emitting control unit comprises a second thin film transistor, a gate of the second thin film transistor is connected to a second light emitting control signal, a first end of the second thin film transistor, a second end of the first thin film transistor, and the light emitting device are coupled to a third node, and a second end of the second thin film transistor is electrically connected to a node of a sub-pixel driving circuit of an adjacent row of the sub-pixels connected to a same data signal line.
20. The display terminal according to claim 19 , wherein a potential of the first light emitting control signal and a potential of the second light emitting control signal are opposite.