Arithmetic device and electronic device
An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.
1. An arithmetic device comprising:
a first arithmetic portion; and
a second arithmetic portion,
wherein the first arithmetic portion comprises a first central processing unit (CPU) core and a second CPU core,
wherein the second arithmetic portion comprises a first graphics processing unit (GPU) core and a second GPU core,
wherein the first CPU core and the second CPU core are each configured to perform power gating,
wherein the first CPU core and the second CPU core each comprise a first data retention circuit electrically connected to a flip-flop,
wherein the first GPU core comprises a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits,
wherein the second GPU core comprises a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit,
wherein the first to third data retention circuits each comprise a first transistor and a capacitor,
wherein the first transistor is electrically connected to the capacitor, and
wherein a channel formation region of the first transistor comprises an oxide semiconductor.
2. The arithmetic device according to claim 1 ,
wherein each of the second data retention circuit and the third data retention circuit further comprises a second transistor, and
wherein a potential corresponding to the analog value or the digital value is retained in a node at which one of a source and a drain of the first transistor, one electrode of the capacitor, and a gate of the second transistor are electrically connected to one another.
3. The arithmetic device according to claim 1 , wherein switching of either one of the first CPU core and the second CPU core to a state of executing arithmetic processing and switching of the other to a state of performing power gating are performed, and the switching is controlled in response to a temperature of a region provided with the first CPU core or the second CPU core.
4. The arithmetic device according to claim 1 , wherein switching of either one of the first GPU core and the second GPU core to a state of executing arithmetic processing and switching of the other to a state of performing power gating are performed, and the switching is controlled in response to whether the arithmetic processing is arithmetic processing on the basis of scientific computation or arithmetic processing on the basis of inference using a neutral network.
5. An electronic device comprising the arithmetic device according to claim 1 .