IP Library › Granted Patent US 11,422,890
Granted Patent B2
US 11,422,890 · App. 16/645,756 · Granted Aug 23, 2022

Quantum error correction

Inventor: Austin Greig Fowler (Reseda, CA)
Assignee: Google LLC
G06F11/1076G06N10/00
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Quick Facts
Patent No.
US 11,422,890
App. No.
16/645,756
Granted
Aug 23, 2022
Kind
B2
Abstract

Methods, systems and apparatus for correcting a stream of syndrome measurements produced by a quantum computer. A layered representation of error propagation through quantum error detection circuits is received. The layered representation includes a plurality of line circuit layers that each represent a probability of local detection events in a quantum computer associated with one or more potential error processes in the execution of a quantum algorithm. During execution of the quantum algorithm, one or more syndrome measurements are received from quantum error detection circuits. The syndrome measurements are converted into detection events and written to an array that represents quantum error correction circuits that are grouped together at a sequence of steps in the quantum algorithm. Errors in the execution of the quantum algorithm are determined from the detection events in dependence upon the stored line circuit layers. Based on the determined errors, the syndrome measurements are corrected.

Claims (62)

1. A method of correcting a stream of syndrome measurements produced by a quantum computer, the method comprising:

receiving a layered representation of error propagation through quantum error detection circuits in the quantum computer, wherein

i) the layered representation comprises a plurality of line circuit layers, each line circuit layer representing a probability of local detection events in the quantum computer associated with one or more potential error processes in an execution of a quantum algorithm, and

ii) the layered representation is constructed prior to execution of the quantum algorithm, wherein constructing the layered representation comprises:

for each of one or more quantum gates in the quantum error correction circuits, determining one or more potential detection events associated with each potential error process occurring at that quantum gate,

associating one or more lines with each potential error process, the lines each connecting a potential detection event associated with the potential error process to another potential detection event associated with the same potential error process or a boundary of the quantum error correction circuits,

merging similar lines to form one or more merged lines, and

constructing the layered representation from a plurality of the merged lines; and

during execution of the quantum algorithm:

receiving one or more syndrome measurements from the quantum error detection circuits in the quantum computer;

converting the one or more syndrome measurements into detection events written to an array, the array representing quantum error correction circuits that are grouped together at a sequence of steps in the quantum algorithm;

determining one or more errors in the execution of the quantum algorithm from the detection events in dependence upon the plurality of line circuit layers; and

causing correction of the one or more syndrome measurements based on the determined one or more errors.

2. The method of claim 1 , wherein the one or more lines are each associated with a weight indicative of the probability of the associated potential error process.

3. The method of claim 2 , wherein the weights are discretised.

4. The method of claim 1 , wherein merging similar lines comprises combining lines of the one or more lines associated with each potential error process having at least one of:

a same start point and a same end point;

a same direction and length; and/or

a common potential error.

5. The method of claim 1 , wherein potential error processes not common to similar lines forming a merged line are removed from association with said merged line.

6. The method of claim 1 , wherein the detection events are cyclically written to the array.

7. The method of claim 6 , wherein the array comprises a plurality of layers, the number of layers in the plurality of layers being a power of two.

8. The method of claim 1 , wherein the array is stored in a processor cache during execution of the quantum algorithm.

9. The method of claim 1 , wherein the array is representative of quantum error correction circuits that are grouped together in the quantum computer.

10. The method of claim 1 , wherein determining the errors in the execution of the quantum computing algorithm comprises using a perfect matching process.

11. The method of claim 1 , wherein determining the errors in the execution of the quantum computing algorithm comprises using a minimum weight perfect matching process to pair the detection events in the array that are connected by one or more lines in one or more of the line circuit layers.

12. The method of claim 1 , wherein determining the errors in the execution of the quantum computing algorithm comprises using a minimum weight perfect matching process to match one or more of the detection events with a boundary of the array.

13. The method of claim 1 , wherein determining the errors in the execution of the quantum computing algorithm comprises at least one of:

exploring the array around a selected detection event to find an untouched detection event and pairing the selected detection event with the untouched detection event; and/or

exploring the array around a selected detection event to find a previously explored region associated with a different detection event and pairing the selected detection event with the different detection event.

14. The method of claim 13 , wherein the exploring of the array around a selected detection event is guided by the line circuit layers.

15. The method of claim 1 , wherein the layered representation is constructed by a separate computer.

16. A system comprising:

a quantum computer for executing a quantum algorithm comprising a plurality of quantum error detection circuits; and

one or more classical processing cores,

wherein a set of one or more classical processing cores are configured to perform operations comprising:

receiving a layered representation of error propagation through quantum error detection circuits in the quantum computer, wherein

i) the layered representation comprises a plurality of line circuit layers, each line circuit layer representing a probability of local detection events in the quantum computer associated with one or more potential error processes in an execution of a quantum algorithm, and

ii) the layered representation is constructed prior to execution of the quantum algorithm, wherein constructing the layered representation comprises:

for each of one or more quantum gates in the quantum error correction circuits, determining one or more potential detection events associated with each potential error process occurring at that quantum gate,

associating one or more lines with each potential error process, the lines each connecting a potential detection event associated with the potential error process to another potential detection event associated with the same potential error process or a boundary of the quantum error correction circuits,

merging similar lines to form one or more merged lines, and

constructing the layered representation from a plurality of the merged lines; and

during execution of the quantum algorithm:

receiving one or more syndrome measurements from the quantum error detection circuits in the quantum computer;

converting the one or more syndrome measurements into detection events written to an array, the array representing quantum error correction circuits that are grouped together at a sequence of steps in the quantum algorithm;

determining one or more errors in the execution of the quantum algorithm from the detection events in dependence upon the plurality of line circuit layers; and

causing correction of the one or more syndrome measurements based on the determined one or more errors.

17. The system of claim 16 , further comprising a further one or more classical processing cores configured to construct the layered representation of error propagation through quantum error detection circuits in the quantum computer.

18. A computer program product comprising a non-transitory computer readable medium containing program instructions for causing a processing core to perform operations comprising:

receiving a layered representation of error propagation through quantum error detection circuits in a quantum computer, wherein

i) the layered representation comprises a plurality of line circuit layers, each line circuit layer representing a probability of local detection events in the quantum computer associated with one or more potential error processes in an execution of a quantum algorithm, and

ii) the layered representation is constructed prior to execution of the quantum algorithm, wherein constructing the layered representation comprises:

for each of one or more quantum gates in the quantum error correction circuits, determining one or more potential detection events associated with each potential error process occurring at that quantum gate,

associating one or more lines with each potential error process, the lines each connecting a potential detection event associated with the potential error process to another potential detection event associated with the same potential error process or a boundary of the quantum error correction circuits,

merging similar lines to form one or more merged lines, and

constructing the layered representation from a plurality of the merged lines; and

during execution of the quantum algorithm:

receiving one or more syndrome measurements from the quantum error detection circuits in the quantum computer;

converting the one or more syndrome measurements into detection events written to an array, the array representing quantum error correction circuits that are grouped together at a sequence of steps in the quantum algorithm;

determining one or more errors in the execution of the quantum algorithm from the detection events in dependence upon the plurality of line circuit layers; and

causing correction of the one or more syndrome measurements based on the determined one or more errors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: FOWLER, AUSTIN GREIG
To: GOOGLE LLC
Reel/Frame 052274/0340 →
Continuity (1)
Related Publication 20200285539A1 · Sep 10, 2020