Quantum dot devices
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.
1. A quantum dot device, comprising:
a quantum well stack including a quantum well layer; and
a plurality of gates above the quantum well stack, wherein individual gates include a gate dielectric and a gate metal, the gate metal of adjacent gates is spaced apart by insulating material, and top surfaces of the gate metal of individual gates are dished.
2. The quantum dot device of claim 1 , wherein the gate dielectric of individual gates extends up adjacent sidewalls of the insulating material.
3. The quantum dot device of claim 1 , wherein the insulating material is a spacer material.
4. The quantum dot device of claim 1 , wherein the insulating material is an interlayer dielectric.
5. The quantum dot device of claim 1 , wherein the gate metal includes a superconductor.
6. The quantum dot device of claim 1 , wherein the quantum well layer includes silicon or germanium.
7. The quantum dot device of claim 1 , wherein the gate dielectric is on the quantum well layer.
8. The quantum dot device according to claim 1 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the quantum well stack and the plurality of gates,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the plurality of gates during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
9. The quantum dot device of claim 8 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
10. The quantum dot device of claim 8 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
11. A quantum dot device, comprising:
a quantum well stack including a quantum well layer; and
a plurality of gates above the quantum well stack, wherein individual gates include a gate dielectric and a gate metal, the gate metal of adjacent gates is spaced apart by an insulating material, and the insulating material is an interlayer dielectric.
12. The quantum dot device of claim 11 , wherein a continuous portion of the gate dielectric provides the gate dielectric for multiple ones of the individual gates.
13. The quantum dot device of claim 11 , wherein a width of the gate metal of individual gates is greater proximate to the quantum well stack than distal to the quantum well stack.
14. The quantum dot device of claim 11 , wherein the interlayer dielectric includes silicon.
15. The quantum dot device of claim 14 , wherein the interlayer dielectric further includes oxygen or nitrogen.
16. The quantum dot device of claim 11 , wherein the interlayer dielectric includes aluminum.
17. The quantum dot device of claim 11 , wherein the interlayer dielectric includes carbon.
18. The quantum dot device of claim 11 , wherein the quantum well stack includes a barrier layer, and the gate dielectric is spaced apart from the quantum well layer by the barrier layer.
19. The quantum dot device according to claim 11 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the quantum well stack and the plurality of gates,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the plurality of gates during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
20. The quantum dot device of claim 19 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.