Feeder design with high current capability
A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material, comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material wherein the at least two p-type grids are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material between the first and a second regions without any grids.
1. A PiN diode structure in a SiC semiconductor material comprising an n-type substrate, a drift layer on the n-type substrate, an n-type SiC material on the drift layer, and at least two p-type grids in the n-type SiC material, wherein the PiN diode structure comprises:
at least one epitaxially grown p-type region;
an n-type epitaxially grown layer of SiC disposed in contact with the at least two p-type grids and the n-type SiC material and disposed in contact with the at least one epitaxially grown p-type region; and
an Ohmic contact disposed in contact with the at least one epitaxially grown p-type region,
wherein a projection of the at least one epitaxially grown p-type region in a plane parallel with the n-type substrate has a boundary line limiting the projection of the at least one epitaxially grown p-type region,
wherein the at least two p-type grids are disposed at least so that a projection of the at least two p-type grids in a plane parallel to the n-type substrate is in a surrounding of the boundary line, so that the distance from the boundary line to any point in the surrounding is maximum 0.5 μm, and
wherein the at least two p-type grids also are disposed only so that the distance from the lower part of the at least one epitaxially grown p-type region to the upper part of the at least two p-type grid is in the range of 0 μm to 5 μm, the direction up being given by the direction perpendicular away from the n-type substrate.
2. The structure according to claim 1 , wherein the at least one epitaxially grown p-type region is disposed in contact with at least one of the at least two p-type grids.
3. The structure according to claim 1 , wherein the at least one epitaxially grown p-type region is not disposed in contact with the at least two p-type grids.
4. The structure according to claim 1 , wherein the at least two p-type grids each comprises a plurality of ion implanted grids.
5. The structure according to claim 1 , wherein the width of the at least one epitaxially grown p-type region is in the interval 5 μm to 500 μm.
6. The structure according to claim 1 , wherein the thickness of the at least one epitaxially grown p-type region is in the interval 1 μm to 3 μm.
7. The structure according to claim 1 , wherein the doping concentration of the at least one epitaxially grown p-type region varies from closest to the n-type SiC material to closest to the Ohmic contact.
8. The structure according to claim 7 , wherein the doping concentration of the at least one epitaxially grown p-type region is highest closest to the Ohmic contact.
9. The structure according to claim 8 , wherein the doping concentration of the at least one epitaxially grown p-type region is in the interval 5e17 cm −3 to 1e19 cm −3 except in a layer closest to the Ohmic contact where it is in the interval 1e19 cm −3 to 3e20 cm −3 .
10. The structure according to claim 1 , wherein there is a space between the at least one epitaxially grown p-type region and the at least two p-type grids in the n-type SiC material, and wherein a connection is disposed between the at least one epitaxially grown p-type region and the at least two p-type grids.
11. The structure according to claim 1 , wherein the at least one epitaxially grown p-type region is applied directly on the at least two p-type grids in the n-type SiC material.
12. The structure according to claim 1 , wherein the doping concentration of the at least two p-type grids is in the interval of 3e17 cm −3 to 3e20 cm −3 , wherein the thickness of the at least two p-type grids is in the interval of 0.5 μm to 2.5 μm, and wherein the width of each of the at least two p-type grids is at least 0.5 μm.
13. The structure according to claim 1 , wherein there are at least three of the at least two p-type grids, and wherein the space between two adjacent p-type grids is in the interval of 1 μm to 5 μm, not taking into account the region in the n-type SiC material between the first region and a second region without any grids as a space.
14. The structure according to claim 1 , wherein the thickness of the epitaxially grown n-type layer is at least 0.5 μm; and wherein the doping concentration is in the interval of 1e14 cm −3 and 1e17 cm −3 .
15. The structure according to claim 1 , wherein the thickness of the epitaxially grown n-type layer is at least 0.5 μm thicker than the at least one epitaxially grown p-type region.
16. The structure according to claim 1 , wherein the at least two p-type grids comprise a plurality of grids, wherein at least a part of the grids has a ledge positioned centered under the grids, the ledge positioned in a direction away from the n-type epitaxially grown layer, the ledge having a smaller lateral dimension than the grids.
17. The structure according to claim 1 , wherein the at least two p-type grids comprise a plurality of grids; wherein each grid comprises an upper part and a lower part, the upper part being towards the n-type epitaxially grown layer; wherein the upper part is manufactured using epitaxial growth; and wherein the lower part is manufactured using ion implantation.
18. The structure according to claim 1 , wherein the at least two p-type grids are manufactured by ion implantation.
19. A device comprising a structure according to claim 1 .
20. The device according to claim 19 , wherein the device is selected from the group consisting of a MOSFET, a JFET, a JBS diode, and an insulated-gate bipolar transistor (IGBT).
21. The device according to claim 20 , wherein the device is an integration of at least two components.
22. A method for the manufacture of a structure in SiC according to claim 1 comprising the steps of:
a) providing a substrate with a drift layer and an n-type SiC material on top,
b) adding a p-type layer by epitaxial growth of SiC,
c) etching away unwanted parts of the added p-type layer to obtain at least one epitaxially grown p-type region,
d) creating at least two p-type grids in the n-type SiC material,
e) adding an n-type layer by epitaxial growth of SiC.
23. The method according to claim 22 , wherein step d) is carried out before step b).
24. The method according to claim 22 , wherein step d) is carried out by ion implantation.
25. The method according to claim 24 , wherein the steps are carried out in the order: a), d), e), b), c) with an additional step of etching a trench in the n-type layer after step e), in a region intended for the at least one epitaxially grown p-type region.