Systems and methods of efficiently interrupting virtual machines

1. A computing device comprising:

a memory;

at least one processor coupled to the memory and configured to

execute a lightweight virtual machine monitor (VMM),

execute a virtual machine under control of the lightweight VMM, and

generate, via execution of the lightweight VMM, a self inter-processor interrupt (IPI) comprising an identifier of an external interrupt; and

an advanced programmable interrupt controller (APIC) comprised within the at least one processor and configured to

receive the self IPI,

identify the external interrupt, and

deliver the external interrupt to the virtual machine.

2. The computing device of claim 1 , wherein the lightweight VMM is further configured to virtualize hardware other than the APIC.

3. The computing device of claim 2 , wherein the lightweight VMM is further configured to:

allocate a first virtual machine control structure (VMCS) to manage execution of the virtual machine;

allocate a second VMCS to manage execution of the lightweight VMM, the second VMCS comprising a Pin-Based VM-Execution Controls field; and

write a value of 0 in bit[ 0 ] of the Pin-Based VM-Execution Controls field of the second VMCS.

4. The computing device of claim 1 , wherein the lightweight VMM is further configured to initiate execution of the virtual machine.

5. The computing device of claim 1 , wherein the APIC comprises and interrupt command register (ICR) and the lightweight VMM is configured to generate the self IPI at least in part by writing one or more values to the ICR.

6. The computing device of claim 1 , wherein the virtual machine comprises an interrupt descriptor table (IDT), and the APIC is configured to deliver the external interrupt at least in part by writing an identifier of the external interrupt to the IDT.

7. The computing device of claim 1 , wherein the virtual machine is configured to execute an interrupt service routine (ISR) in response to detecting the external interrupt, the ISR being configured to process input data stored at a predefined address within the memory and the lightweight VMM is further configured to:

virtualize the memory;

virtualize the processor without virtualizing the APIC;

receive a notification indicating that input data is available at the predefined address; and

generate the self IPI in response to receiving the notification.

8. The computing device of claim 7 , further comprising a controller area network (CAN) bus controller coupled to a CAN bus and the memory and configured to:

receive the input data via the CAN bus; and

store the input data at the predefined address.

9. The computing device of claim 8 , wherein the CAN bus is disposed within a vehicle.

10. A method of delivering an external interrupt to a virtual machine using a lightweight virtual machine monitor (VMM), the method comprising:

executing, via at least one processor of a computing device, the lightweight VMM;

executing, via the at least one processor of the computing device, a virtual machine under control of the lightweight VMM;

generating, via execution of the lightweight VMM, a self inter-processor interrupt (IPI) comprising an identifier of an external interrupt;

receiving, via an advanced programmable interrupt controller (APIC), the self IPI;

identifying, via the APIC, the external interrupt; and

delivering, via the APIC, the external interrupt to the virtual machine.

11. The method of claim 10 , further comprising:

allocating a first virtual machine control structure (VMCS) to manage execution of the virtual machine;

allocating a second VMCS to manage execution of the lightweight VMM, the second VMCS comprising a Pin-Based VM-Execution Controls field; and

writing a value of 0 in bit[ 0 ] of the Pin-Based VM-Execution Controls field of the second VMCS.

12. The method of claim 10 , wherein:

generating the self IPI comprises writing one or more values to an interrupt command register; and/or

delivering the external interrupt comprises writing an identifier of the external interrupt to an interrupt descriptor table of the virtual machine.

13. The method of claim 10 , further comprising:

virtualizing, via execution of the lightweight VMM, memory of the computing device;

virtualizing, via execution of the lightweight VMM, the processor without virtualizing the APIC;

receiving, via execution of the lightweight VMM, a notification indicating that input data is available at a predefined address within the memory;

generating the self IPI in response to receiving the notification;

executing, via execution of the virtual machine, an interrupt service routine (ISR) in response to detecting the external interrupt; and

processing, via execution of the ISR, input data stored at the predefined address.

14. The method of claim 13 , wherein the input data is received via a controller area network (CAN) bus that is disposed within a vehicle.

15. A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for delivering interrupts to a virtual machine, the process comprising:

executing, via at least one processor of a computing device, a lightweight VMM;

executing, via the at least one processor of the computing device, a virtual machine under control of the lightweight VMM;

generating, via execution of the lightweight VMM, a self inter-processor interrupt (IPI) comprising an identifier of an external interrupt;

receiving, via an advanced programmable interrupt controller (APIC), the self IPI;

identifying, via the APIC, the external interrupt; and

delivering, via the APIC, the external interrupt to the virtual machine.

16. The computer program product of claim 15 , wherein the process further comprises:

allocating a first virtual machine control structure (VMCS) to manage execution of the virtual machine;

allocating a second VMCS to manage execution of the lightweight VMM, the second VMCS comprising a Pin-Based VM-Execution Controls field; and

writing a value of 0 in bit[ 0 ] of the Pin-Based VM-Execution Controls field of the second VMCS.

17. The computer program product of claim 15 , wherein:

generating the self IPI comprises writing one or more values to an interrupt command register; and/or

delivering the external interrupt comprises writing an identifier of the external interrupt to an interrupt descriptor table of the virtual machine.

18. The computer program product of claim 15 , wherein the process further comprises:

virtualizing, via execution of the lightweight VMM, memory of the computing device;

virtualizing, via execution of the lightweight VMM, the processor without virtualizing the APIC;

receiving, via execution of the lightweight VMM, a notification indicating that input data is available at a predefined address within the memory;

generating the self IPI in response to receiving the notification;

executing, via execution of the virtual machine, an interrupt service routine (ISR) in response to detecting the external interrupt; and

processing, via execution of the ISR, input data stored at the predefined address.

19. The computer program product of claim 18 , wherein the process further comprises:

receiving the input data via a controller area network (CANS bus; and

storing the input data at the predefined address.

20. The computer program product of claim 19 , wherein the CAN bus is disposed within a vehicle.