Field effect transistors with reduced electric field by thickening dielectric on the drain side

1. An integrated circuit device structure comprising:

a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material; and

a gate dielectric over at least a portion of the channel region, wherein the gate dielectric has a first gate dielectric, and a second gate dielectric layer on the first gate dielectric layer, wherein the first gate dielectric has a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the first gate dielectric has a linearly varied thickness over the channel region.

2. The integrated circuit device structure of claim 1 , wherein the second gate dielectric layer has a third thickness proximate to the source and a fourth thickness proximate to the drain, wherein the fourth thickness is greater than the third thickness, and wherein at least a portion of the second gate dielectric layer over the channel region has a linearly varied thickness.

3. The integrated circuit device structure of claim 2 , wherein a top surface of the second gate dielectric layer is substantially parallel with a top surface of the channel region.

4. The integrated circuit device structure of claim 1 , wherein the first gate dielectric layer comprises a first material with a first dielectric constant, the second gate dielectric layer comprises a second material with a second dielectric constant, and wherein the first dielectric constant is less than the second dielectric constant.

5. The integrated circuit device structure of claim 1 , wherein the gate dielectric is over a side of the channel region.

6. The integrated circuit device structure of claim 1 , wherein the channel region comprises germanium.

7. A method of forming an integrated circuit device structure comprising:

forming a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material; and

forming a gate dielectric over at least a portion of the channel region, wherein the gate dielectric has a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric has a linearly varied thicknesses between the first thickness and the second thickness, wherein forming the gate dielectric comprises at least one of:

oxidizing the channel region to form an oxide layer of the second thickness; and

plasma etching the oxide layer at an angle to form the first thickness; or

depositing a dielectric material of the second thickness on the channel region; and

plasma etching the dielectric material at an angle to form the first thickness.

8. The method of claim 7 , wherein forming the gate dielectric comprises:

depositing a first layer of dielectric material up to the first thickness on the channel region;

depositing a second layer of dielectric material up to the second thickness on a second length of the first layer of dielectric material; and

plasma etching the dielectric material at an angle to form a third thickness.

9. The method of claim 7 , further comprising forming the gate dielectric over a side of the channel region.

10. The method of claim 7 , wherein forming the gate dielectric comprises forming a first gate dielectric layer on the channel region and forming a second gate dielectric layer on the first gate dielectric layer, wherein the first gate dielectric layer comprises a first material having a first dielectric constant less than a second dielectric constant of a second material of the second gate dielectric layer.