Resistive memory device with meshed electrodes
A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.
1. A semiconductor structure for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array, the semiconductor structure comprising:
a conductive line constructed within an interlayer dielectric (ILD);
a barrier layer disposed over a portion of the conductive line;
a bottom meshed electrode;
a dielectric layer disposed over the bottom meshed electrode; and
a top meshed electrode disposed over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.
2. The semiconductor structure of claim 1 , wherein the plurality of isolation films of the bottom meshed electrode are perpendicular to the plurality of isolation films of the top meshed electrode.
3. The semiconductor structure of claim 1 , wherein the plurality of isolation films are formed from silicon nitride (SiN).
4. The semiconductor structure of claim 1 , wherein a metal layer is disposed over the top meshed electrode.
5. The semiconductor structure of claim 4 , wherein the bottom meshed electrode, the dielectric layer, the top meshed electrode, and the metal layer define the RRAM stack.
6. The semiconductor structure of claim 5 , wherein spacers are formed adjacent the RRAM stack.
7. The semiconductor structure of claim 1 , wherein the top and bottom meshed electrodes are formed from a same material.
8. The semiconductor structure of claim 7 , wherein the same material is titanium oxynitride (TiON).
9. The semiconductor structure of claim 1 , wherein the barrier layer is a tantalum nitride (TaN) layer and the conductive line is a copper (Cu) line.
10. The semiconductor structure of claim 1 , wherein the top and bottom meshed electrodes include a high resistivity to localize filament formation.
11. A semiconductor structure for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array, the semiconductor structure comprising:
a bottom meshed electrode;
a dielectric layer disposed over the bottom meshed electrode; and
a top meshed electrode disposed over the dielectric layer, where the bottom meshed electrode includes a plurality of first isolations films.
12. The semiconductor structure of claim 11 , wherein the top meshed electrode includes a plurality of second isolations films.
13. The semiconductor structure of claim 12 , wherein a conductive line is constructed within an interlayer dielectric (ILD).
14. The semiconductor structure of claim 13 , wherein a barrier layer is disposed over a portion of the conductive line.
15. The semiconductor structure of claim 14 , wherein the bottom meshed electrode directly contacts the barrier layer.
16. The semiconductor structure of claim 15 , wherein the plurality of first isolation films of the bottom meshed electrode are perpendicular to the plurality of second isolation films of the top meshed electrode.
17. The semiconductor structure of claim 16 , wherein the plurality of first and second isolation films are formed from silicon nitride (SiN).
18. The semiconductor structure of claim 17 , wherein a metal layer is disposed over the top meshed electrode.
19. The semiconductor structure of claim 18 , wherein spacers are formed adjacent the RRAM stack.
20. The semiconductor structure of claim 19 , wherein the top and bottom meshed electrodes are formed from a same material.