Field effect transistor (FET) comprising channels with silicon germanium (SiGe)
A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.
1. A device comprising:
a substrate; and
a first transistor formed over the substrate, the first transistor comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe);
a plurality of inner spacers located between the first source and the first drain;
a first gate surrounding the first plurality of channels; and
a bottom silicon germanium (SiGe) layer located in the substrate.
2. The device of claim 1 , wherein the at least one channel comprising silicon germanium (SiGe) includes a germanium concentration in a range of about 2-8 percent (%).
3. The device of claim 1 ,
wherein the first source and the first drain, each includes N type dopant (N+), and
wherein the first transistor is configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor.
4. The device of claim 1 ,
wherein the first source and the first drain, each includes P type dopant (P+), and
wherein the first transistor is configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.
5. The device of claim 1 , wherein a minimum voltage required to induce a current flow in the first transistor is approximately 0.3 volts (V).
6. The device structure of claim 1 , wherein each channel from the first plurality of channels has a channel thickness of approximately 5-10 nanometers (nm).
7. The device of claim 1 , further comprising a high K dielectric layer between a channel and the first gate.
8. The device of claim 7 , further comprising a titanium nitride (TiN) layer between a channel and the first gate.
9. The device of claim 8 , further comprising a work metal layer between a channel and the first gate.
10. The device of claim 1 , wherein the device is incorporated into an electronic device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
11. The device of claim 1 , wherein the bottom silicon germanium (SiGe) layer is part of the plurality of channels of the first transistor.
12. The device of claim 1 , wherein the bottom silicon germanium (SiGe) layer is located under a channel from the first plurality of channels.
13. The device of claim 1 , further comprising a high k dielectric layer, a metal layer, and/or a work function metal layer, located between the bottom silicon germanium (SiGe) layer and the first gate.
14. The device of claim 1 , wherein the plurality of inner spacers comprises:
a first inner spacer located between a first channel and the first source; and
a second inner spacer located between the first channel and the first drain.
15. An integrated device comprising:
a substrate;
a first transistor formed over the substrate, the first transistor comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe),
a first plurality of inner spacers located between the first source and the first drain;
a first gate surrounding the first plurality of channels; and
a first bottom silicon germanium (SiGe) layer located in the substrate, wherein the first bottom silicon germanium (SiGe) layer is located under a channel from the first plurality of channels; and
a second transistor formed over the substrate, the second transistor comprising:
a second source disposed over the substrate;
a second drain disposed over the substrate;
a second plurality of channels coupled to the second source and the second drain,
wherein the second plurality of channels is located between the second source and the second drain, and
wherein at least one channel from the second plurality of channels comprises silicon germanium (SiGe);
a second plurality of inner spacers located between the second source and the second drain;
a second gate surrounding the second plurality of channels; and
a second bottom silicon germanium (SiGe) layer located in the substrate, wherein the second bottom silicon germanium (SiGe) layer is located under a channel from the second plurality of channels.
16. The integrated device of claim 15 , wherein the at least one channel comprising silicon germanium (SiGe) includes a germanium concentration in a range of about 2-8 percent (%).
17. The integrated device of claim 15 ,
wherein the first transistor configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor, and
wherein the second transistor configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.
18. The integrated device of claim 17 ,
wherein the first transistor further comprises a first titanium nitride (TiN) layer between the first gate and a channel from the first plurality of channels, the first TiN layer having a first thickness,
wherein the second transistor further comprises a second titanium nitride (TiN) layer between the second gate and a channel from the second plurality of channels, the second TiN layer having a second thickness, and
wherein the second thickness of the second TiN layer is greater than the first thickness of the first TiN layer.
19. The integrated device of claim 15 ,
wherein the substrate includes a P-well and a N-well,
wherein the first transistor is formed over the P well of the substrate, and
wherein the second transistor is formed over the N well of the substrate.
20. The integrated device of claim 15 , wherein the first gate and the second gate are different gates.
21. The integrated device of claim 15 , wherein the first gate and the second gate are part of the same gate.
22. The integrated device of claim 15 , wherein the first transistor and the second transistor are configured to form a complementary metal-oxide-semiconductor (CMOS) structure.
23. The integrated device of claim 15 , wherein the integrated device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
24. An apparatus comprising:
a substrate;
a first transistor means formed over the substrate, the first transistor means comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe);
a first plurality of inner spacers located between the first source and the first drain; and
a first gate surrounding the first plurality of channels; and
a first bottom silicon germanium (SiGe) layer located in the substrate, wherein the first bottom silicon germanium (SiGe) layer is located under a channel from the first plurality of channels; and
a second transistor means formed over the substrate, the second transistor means comprising:
a second source disposed over the substrate;
a second drain disposed over the substrate;
a second plurality of channels coupled to the second source and the second drain,
wherein the second plurality of channels is located between the second source and the second drain, and
wherein at least one channel from the second plurality of channels comprises silicon germanium (SiGe);
a second plurality of inner spacers located between the second source and the second drain; and
a second gate surrounding the second plurality of channels; and
a second bottom silicon germanium (SiGe) layer located in the substrate, wherein the second bottom silicon germanium (SiGe) layer is located under a channel from the second plurality of channels.
25. The apparatus of claim 24 , wherein the at least one channel comprising silicon germanium (SiGe) includes a germanium concentration in a range of about 2-8 percent (%).
26. The apparatus of claim 24 ,
wherein the first transistor means is configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor, and
wherein the second transistor means is configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.
27. The apparatus of claim 26 ,
wherein the first transistor means further comprises a first titanium nitride (TiN) layer between the first gate and a channel from the first plurality of channels, the first TiN layer having a first thickness,
wherein the second transistor means further comprises a second titanium nitride (TiN) layer between the second gate and a channel from the second plurality of channels, the second TiN layer having a second thickness, and
wherein the second thickness of the second TiN layer is greater than the first thickness of the first TiN layer.
28. The apparatus of claim 24 ,
wherein the substrate includes a P-well and a N-well,
wherein the first transistor means is formed over the P well of the substrate, and
wherein the second transistor means is formed over the N well of the substrate.
29. The apparatus of claim 24 , wherein the first transistor means and the second transistor means are configured to form a complementary metal-oxide-semiconductor (CMOS) structure.
30. The apparatus of claim 24 , wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
31. A method for fabricating an integrated device, comprising:
providing a substrate; and
forming a first transistor over the substrate, wherein forming the first transistor comprises:
forming a bottom silicon germanium (SiGe) layer in the substrate;
forming a first source over the substrate;
forming a first drain over the substrate;
forming a first plurality of channels between the first source and the first drain, wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe);
forming a first plurality of inner spacers between the first source and the first drain; and
forming a first gate surrounding the first plurality of channels.
32. The method of claim 31 , wherein forming the first plurality of channels comprises forming at least one channel comprising silicon germanium (SiGe) having a germanium concentration in a range of about 2-8 percent (%).
33. The method of claim 31 , further forming a second transistor over the substrate, wherein forming the second transistor comprises:
forming a second source over the substrate;
forming a second drain over the substrate;
forming a second plurality of channels between the second source and the second drain, wherein at least one channel from the second plurality of channels comprises silicon germanium (SiGe);
forming a second plurality of inner spacers between the second source and the second drain; and
forming a second gate surrounding the second plurality of channels.
34. The method of claim 33 , wherein the first gate and the second gate are part of the same gate.