Self-tuning digital clock generator

1. A clock generator, comprising:

a ring oscillator including an input and an output;

a count circuit including an input and an output, wherein the input of the count circuit is coupled to the output of the ring oscillator;

a comparator including a first input, a second input, and an output, wherein the first input of the comparator is configured to receive a first count value, and the second input of the comparator is coupled to the output of the count circuit; and

a shift register including a shift control input and an output, wherein the shift control input is coupled to the output of the comparator, and the output of the shift register is coupled to the input of the ring oscillator;

wherein the shift register is configured to shift control values in the shift register in a first direction if a first value is input to the shift control input, shift the control values in the shift register in a second direction if a second value is input to the shift control input, wherein the first direction is opposite the second direction, and output the control values at the output of the shift register.

2. A clock generator, comprising:

a ring oscillator including multiple control inputs and an output;

a count circuit including an input and an output, wherein the input of the count circuit is coupled to the output of the ring oscillator;

a comparator including a first input, a second input, and an output, wherein the first input of the comparator is configured to receive a first count value, and the second input of the comparator is coupled to the output of the count circuit; and

a shift register including a shift control input coupled to the output of the comparator, wherein the shift register comprises multiple storage elements, and each of the storage elements is coupled to a respective one of the multiple control inputs of the ring oscillator.

3. The clock generator of claim 2 , wherein:

the ring oscillator comprises multiple multiplexers; and

each of the multiplexers includes a respective one of the control inputs, a first input, a second input, and an output, wherein the first input is coupled to the output of another one of the multiplexers, and the second input is coupled to a bypass signal path.

4. The clock generator of claim 2 , wherein the multiple storage elements are configured to store control values, and the shift register further comprises a shift controller configured to shift the control values in the multiple storage elements in a first direction or a second detection based on a shift control signal input to the shift control input, wherein the first direction is opposite the second direction.

5. The clock generator of claim 4 , wherein the shift controller is configured to shift the control values in the first direction if the shift control signal has a first value, and shift the control values in the second direction if the shift control signal has a second value.

6. The clock generator of claim 2 , further comprising a glitch circuit, wherein the glitch circuit comprises:

multiple latches, wherein each of the multiple latches includes a latch input coupled to a respective one of the multiple storage elements, an output coupled to a respective one of the control inputs of the ring oscillator, and a clock input; and

a timing circuit configured to receive a clock signal from the ring oscillator, delay the received clock signal by a time delay to generate a timing signal, and output the timing signal to the clock input of each of one or more of the latches.

7. The clock generator of claim 6 , wherein the time delay is approximately equal to a quarter of a period of the clock signal.

8. The clock generator of claim 1 , wherein the ring oscillator is configured to output a clock signal at the output of the ring oscillator, and the count circuit is configured to:

count periods of the clock signal over a count window to generate a second count value; and

output the second count value at the output of the count circuit.

9. The clock generator of claim 8 , wherein the comparator is configured to:

compare the first count value with the second count value;

generate a shift control signal based on the comparison; and

output the shift control signal at the output of the comparator.

10. The clock generator of claim 8 , wherein the ring oscillator is configured to control a frequency of the clock signal based on the control values.

11. The clock generator of claim 9 , wherein

the shift control signal has the first value if the second count value is greater than the first count value; and

the shift register is configured to shift the control values in the shift register in a first direction if the shift control signal has the first value.

12. The clock generator of claim 11 , wherein

the shift control signal has the second value if the second count value is less than the first count value.

13. A method for controlling a ring oscillator, comprising:

receiving a clock signal from the ring oscillator;

counting periods of the clock signal over a count time window to generate a count value;

comparing the generated count value with a target count value;

shifting control values in a shift register based on the comparison; and

outputting the control values in the shift register to the ring oscillator, wherein the ring oscillator generates the clock signal based on the control values;

wherein shifting the control values in the shift register comprises:

shifting the control values in the shift register in a first shift direction if the generated count value is greater than the target count value; and

shifting the control values in the shift register in a second shift direction if the generated count value is less than the target count value, wherein the second shift direction is opposite the first shift direction.

14. The method of claim 13 , wherein outputting the control values in the shift register to the ring oscillator comprises outputting the control values in the shift register to the ring oscillator in parallel.

15. The method of claim 13 , wherein outputting the control values in the shift register to the ring oscillator comprises:

receiving the control values in the shift register; and

outputting the received control values to the ring oscillator within a glitch-free time window.

16. The method of claim 13 , wherein outputting the control values in the shift register to the ring oscillator comprises:

latching the control values in the shift register within a glitch-free time window; and

outputting the latched control values to the ring oscillator.

17. The method of claim 13 , wherein the ring oscillator comprises a chain of multiplexers, and outputting the control values in the shift register to the ring oscillator comprises:

outputting each of the control values to a respective one of the multiplexers, wherein the control values control a frequency of the clock signal by controlling a number of the multiplexers through which an oscillator signal of the ring oscillator propagates.

18. The method of claim 17 , wherein the target count value corresponds to a target frequency.

19. An apparatus for controlling a ring oscillator, comprising:

means for receiving a clock signal from the ring oscillator;

means for counting periods of the clock signal over a count time window to generate a count value;

means for comparing the generated count value with a target count value;

means for shifting control values in a shift register based on the comparison; and

means for outputting the control values in the shift register to the ring oscillator, wherein the ring oscillator generates the clock signal based on the control values;

wherein the means for shifting the control values in the shift register comprises:

means for shifting the control values in the shift register in a first shift direction if the generated count value is greater than the target count value; and

means for shifting the control values in the shift register in a second shift direction if the generated count value is less than the target count value, wherein the second shift direction is opposite the first shift direction.