PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES
A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.
1 . A method, comprising:
coupling a conductive spacer block to a carrier;
coupling a solder or sinter material layer to the conductive spacer block;
coupling a device die to the solder or sinter material layer;
reflowing the solder material or sintering the sinter material to bond the device die and the conductive spacer block to form the vertical device stack; and
removing the vertical device stack from the carrier as a single pre-formed unit.
2 . The method of claim 1 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).
3 . The method of claim 1 , wherein the device die is about 100 microns thick or less.
4 . The method of claim 3 , wherein the device die includes a power device having a size that is greater than 25 square millimeters.
5 . The method of claim 1 , wherein the conductive spacer block has thickness in a range of about 100 microns to 2500 microns, and wherein the solder or sinter material layer has thickness of about 50 microns to 300 microns.
6 . A method, method comprising:
placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof;
placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer;
activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer; and
singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.
7 . The method of claim 6 further comprising:
depositing a passivation layer on exposed sides of the singulated vertical device stacks in a wafer-level deposition process.
8 . The method of claim 6 , wherein activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer includes at least one of pressure sintering, solder reflow, and fusion bonding.
9 . The method of claim 6 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).
10 . The method of claim 6 , wherein the device die is about 100 microns thick or less.
11 . The method of claim 6 , wherein the device die includes a power device having a size that is greater than 25 square millimeters.
12 . The method of claim 6 , wherein the conductive spacer block has thickness in a range of about 100 microns to 2500 microns, and wherein the coupling mechanism material has thickness in a range of about 50 microns to 300 microns.
13 . A method, comprising:
placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof;
placing a one-piece grid of conductive spacer blocks on the coupling mechanism material layer on the backside of the selected wafer;
activating the coupling mechanism material layer to bond the conductive spacer blocks in the one-piece grid of conductive spacer blocks to the backside of the selected wafer; and
singulating the wafer to separate vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.
14 . The method of claim 13 , wherein each conductive spacer block in the one-piece grid of conductive spacer blocks is connected to an adjacent spacer block by a connecting strip, and wherein the connecting strips mechanically hold together the conductive spacer blocks in the grid of conductive spacer blocks as a single piece or unit.
15 . The method of claim 14 , wherein singulating the wafer to separate the vertical device stacks includes cutting or breaking the connecting strips that mechanically hold together the conductive spacer blocks in the grid of conductive spacer blocks as a single piece or unit.
16 . The method of claim 13 further comprising, depositing a passivation layer on the exposed sides of the singulated vertical device stacks in a wafer-level deposition process.
17 . The method of claim 13 , wherein activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer includes at least one of pressure sintering, solder reflow and fusion bonding.
18 . The method of claim 13 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).
19 . The method of claim 13 , wherein the device die is about 100 microns thick or less, and includes a power device having a size that is greater than 25 square millimeters.
20 . A pre-formed vertical device stack, comprising:
a vertical arrangement of thin device die having a device fabricated on a front side thereof, the thin device die being about 100 microns thick or less, and including a power device having a size that is greater than 25 square millimeters; and
a conductive spacer block bonded to a backside of the thin device die via a coupling mechanism,
the conductive spacer block having a thickness greater than about 200 microns,
the conductive spacer block bonded to the thin device die reinforcing a mechanical strength of the thin device die,
the vertical device stack being configured to be moved and placed in a circuit package as a single pre-formed unit.
21 . The pre-formed vertical device stack of claim 20 , further comprising a passivation layer deposited on an exposed side of thereof.