Calibration circuit and calibration apparatus including the same
A system may include: a first memory device; a second memory device; a third memory device; and a fourth memory device, wherein the first memory device to the fourth memory device are configured to share a resistor for impedance matching, wherein the first memory device to the fourth memory device are coupled to have a chain shape, wherein the forth memory device generates a completion signal when performance is completed and the first memory device receives the completion signal provided from the fourth memory device.
1. A system comprising:
a first non-volatile memory device;
a second non-volatile memory device;
a third non-volatile memory device; and
a fourth non-volatile memory device,
wherein the first non-volatile memory device to the fourth non-volatile memory device are configured to share a resistor for impedance matching,
wherein the first non-volatile memory device to the fourth non-volatile memory device are coupled to have a chain shape,
wherein the fourth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the fourth non-volatile memory device.
2. The non-volatile memory device according to claim 1 , wherein at least one of the first non-volatile memory device to the fourth non-volatile memory device includes a volatile memory.
3. The non-volatile memory device according to claim 1 , wherein each non-volatile memory device comprises:
a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, and
a signal generator configured to generate a completion signal when performance is completed.
4. The system according to claim 3 , wherein each non-volatile memory device further comprises:
a command decoder configured to receive the command signal and decode the command signal into a second calibration enable signal; and
a selector configured to select the first completion signal between the first completion signal and the second calibration enable signal according to a select signal, and provide a driving signal,
wherein the second calibration driver is configured to perform the impedance matching operation according to the driving signal.
5. The system according to claim 1 , wherein the non-volatile memory devices sequentially perform the impedance matching operation according to the chain shape.
6. A system comprising:
a first non-volatile memory device to an eighth non-volatile memory device,
wherein the first non-volatile memory device to the eighth non-volatile memory device are configured to share a resistor for impedance matching,
wherein first non-volatile memory device to the eighth non-volatile memory device are coupled to have a chain shape,
wherein the eighth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the eighth non-volatile memory device.
7. The system according to claim 6 , wherein each non-volatile memory device comprises:
a calibration driver configured to perform an impedance matching operation using the resistor for the impedance matching, and
a signal generator configured to generate a completion signal when the performance is completed.
8. The system according to claim 6 , wherein the non-volatile memory devices sequentially perform the impedance matching operation according to the chain shape.
9. The system according to claim 6 , wherein at least one of the non-volatile memory device includes a volatile memory.
10. A system comprising:
a first non-volatile memory device to an sixteenth non-volatile memory device,
wherein the first non-volatile memory device to the sixteenth non-volatile memory device are configured to share a resistor for impedance matching,
wherein the first non-volatile memory device to the sixteenth non-volatile memory device are coupled to have a chain shape,
wherein the sixteenth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the sixteenth non-volatile memory device.
11. The system according to claim 10 , wherein each non-volatile memory device are configured to sequentially perform the impedance matching operation.
12. The system according to claim 10 , wherein each non-volatile memory device includes a calibration driver configured to perform an impedance matching operation by using the resistor and a signal generator configured to generate a status signal when the performance is completed.
13. The system according to claim 10 , wherein the non-volatile memory devices sequentially perform the impedance matching operation according to the chain shape.
14. The system according to claim 10 , wherein at least one of the non-volatile memory devices includes a volatile memory.
15. A system comprising:
a first non-volatile memory device to a thirty-second non-volatile memory device,
wherein the first non-volatile memory device to the thirty-second non-volatile memory device are configured to share a resistor for impedance matching,
wherein the first non-volatile memory device to the thirty-second non-volatile memory device are coupled to have a chain shape,
wherein the thirty-second non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the thirty-second non-volatile memory device.
16. The system according to claim 15 , wherein at least one of the non-volatile memory devices includes a volatile memory.
17. A system comprising:
a first non-volatile memory device;
a second non-volatile memory device;
a third non-volatile memory device; and
a fourth non-volatile memory device,
wherein the first non-volatile memory device to the fourth non-volatile memory device are configured to share a resistor for impedance matching,
wherein the first non-volatile memory device to the fourth non-volatile memory device are coupled to have a chain shape,
wherein at least one of the first non-volatile memory device to the fourth non-volatile memory device includes a volatile memory.
18. The non-volatile memory device according to claim 17 , wherein each non-volatile memory device comprises:
a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, and
a signal generator configured to generate a completion signal when performance is completed.
19. The system according to claim 18 , wherein each non-volatile memory device further comprises:
a command decoder configured to receive the command signal and decode the command signal into a second calibration enable signal; and
a selector configured to select the first completion signal between the first completion signal and the second calibration enable signal according to a select signal, and provide a driving signal,
wherein the second calibration driver is configured to perform the impedance matching operation according to the driving signal.
20. The system according to claim 17 , wherein the non-volatile memory devices sequentially perform the impedance matching operation according to the chain shape.