IP Library Granted Patent US 11,264,264
Granted Patent B2
US 11,264,264 · App. 16/661,686 · Granted Mar 1, 2022

Solder bump formation using wafer with ring

Inventors: Takashi Noma (Ota, JP); Noboru Okubo (Kumagaya, JP); Yusheng Lin (Phoenix, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/68735H01L21/6836H01L21/78H01L24/03H01L24/11H01L24/13H01L24/81H01L29/7393H01L29/861H01L2224/0346H01L2224/1147
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Quick Facts
Patent No.
US 11,264,264
App. No.
16/661,686
Filed
Oct 23, 2019
Granted
Mar 1, 2022
Kind
B2
Art Unit
2815
USPC
257/737
Abstract

At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

Claims (51)

1. A method of making a semiconductor device, comprising:

forming at least one circuit element on a front side of a ringed substrate, an inner portion of a back side of the ringed substrate having been removed to obtain a thinned portion of the ringed substrate with an outer ring of remaining substrate material around a perimeter of the back side of the ringed substrate;

mounting the ringed substrate on a mounting chuck, the mounting chuck having an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein; and

forming at least one solder bump electrically connected to the at least one circuit element, while the ringed substrate is disposed on the mounting chuck.

2. The method of claim 1 , wherein the at least one circuit element includes at least one of a fast recovery diode (FRD) and an insulated gate bipolar transistor (IGBT).

3. The method of claim 1 , further comprising:

forming, prior to the mounting, dual electroless nickel gold (ENIG) plating on, and electrically connected to, the at least one circuit element, and on the inner portion of the back side of the substrate; and

forming the at least one solder bump on, and electrically connected to, the front side ENIG plating.

4. The method of claim 1 , wherein the inner portion is removed including:

securing the front side of the substrate with back side grinding (BG) tape;

grinding the back side of the substrate to define the thinned portion and the outer ring; and

removing the BG tape.

5. The method of claim 1 , wherein the at least one circuit element includes a plurality of circuit elements formed on the front side of the substrate, and wherein forming the at least one solder bump comprises forming a plurality of solder bumps across the substrate and electrically connected to each of the plurality of circuit elements.

6. The method of claim 5 , wherein forming the plurality of solder bumps comprises:

providing a mask over the front side of the substrate while the substrate is mounted on the mounting chuck, the mask having openings over the plurality of circuit elements; and

depositing the plurality of solder bumps through the openings to connect the plurality of solder bumps to the plurality of circuit elements.

7. The method of claim 1 , wherein the thinned portion is less than 300 microns.

8. The method of claim 1 , wherein the at least one solder bump is greater than 150 microns in diameter.

9. The method of claim 1 , further comprising:

removing the ringed substrate from the mounting chuck;

removing the outer ring from the ringed substrate;

dicing the substrate to define individual chips, including at least one chip with the at least one circuit element; and

mounting the at least one circuit element in a flip-chip assembly to at least one circuit board, including electrically connecting the at least one circuit element to the at least one circuit board using the at least one solder bump.

10. A method of making a semiconductor device, comprising:

disposing a wafer on a mounting chuck of a mounting assembly, the wafer having a back side with a ring formed around a perimeter thereof and a thinned portion within the ring, the mounting chuck being disposed on the mounting assembly and including a raised portion configured to receive the thinned portion of the wafer and a recessed portion configured to receive the ring of the wafer; and

forming an electrical connection to the wafer while the wafer is disposed on the mounting chuck with the thinned portion of the wafer on the raised portion of the mounting chuck, and the ring of the wafer disposed within the recessed portion of the mounting chuck.

11. The method of claim 10 , comprising:

forming, prior to the mounting, dual electroless nickel gold (ENIG) plating on at least one circuit element formed on a front side of the wafer that is opposite the back side, and on the thinned portion of the back side; and

forming the electrical connection including at least one solder bump on the front side ENIG plating.

12. The method of claim 10 , wherein the thinned portion and the ring are formed including:

securing a front side of the wafer with back side grinding (BG) tape;

grinding the back side of the wafer to define the thinned portion and the ring; and

removing the BG tape.

13. The method of claim 10 , wherein disposing the wafer comprises:

moving the wafer onto the mounting chuck using a Bernoulli handler.

14. The method of claim 10 , wherein forming the electrical connection comprises:

depositing at least one solder bump for electrical connection to at least one circuit element formed on a front side of the wafer that is opposite the back side.

15. The method of claim 14 , wherein the at least one circuit element includes a plurality of circuit elements formed on the front side, and wherein depositing the at least one solder bump comprises forming a plurality of solder bumps across the wafer and electrically connected to each of the plurality of circuit elements.

16. A method of making a semiconductor device, comprising:

grinding a wafer to form a back side of the wafer with a ring formed around a perimeter thereof and a thinned portion within the ring;

disposing the wafer on a mounting chuck having a raised portion configured to receive the thinned portion of the wafer and a recessed portion configured to receive the ring of the wafer; and

forming at least one electrical connection to a front side of the wafer, opposite the back side, while the wafer is disposed on the mounting chuck.

17. The method of claim 16 , wherein forming the electrical connection comprises:

depositing at least one solder bump for electrical connection to at least one circuit element formed on the front side.

18. The method of claim 17 , wherein the at least one circuit element includes a plurality of circuit elements formed on the front side, and wherein depositing the at least one solder bump comprises forming a plurality of solder bumps across the wafer and electrically connected to each of the plurality of circuit elements.

19. The method of claim 16 , further comprising:

removing the wafer from the mounting chuck;

removing the ring from the wafer;

dicing the wafer to define individual chips; and

mounting at least one circuit element to which the at least one electrical connection is connected in a flip-chip assembly to at least one circuit board, including electrically connecting the at least one circuit element to the at least one circuit board using at least one solder bump.

20. The method of claim 16 , wherein the at least one electrical connection is connected to a fast recovery diode (FRD) and an insulated gate bipolar transistor (IGBT).

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2019
From: NOMA, TAKASHI; OKUBO, NOBORU; LIN, YUSHENG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 050806/0302 →
Continuity (2)
Provisional Application 62878213 · Jul 24, 2019
Related Publication 20210028051A1 · Jan 28, 2021