Semiconductor package
A semiconductor package includes a connection structure including a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a first connection via penetrating through the first insulating layer and connected to the first redistribution layer, a semiconductor chip disposed on the connection structure, an encapsulant covering at least a portion of the semiconductor chip, a second insulating layer disposed on the encapsulant, a second redistribution layer including a signal line disposed on the encapsulant, and a heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line.
1. A semiconductor package comprising:
a connection structure comprising:
a first insulating layer;
a first redistribution layer disposed on the first insulating layer; and
a first connection via penetrating through the first insulating layer and connected to the first redistribution layer;
a semiconductor chip disposed on the connection structure;
an encapsulant covering at least a portion of the semiconductor chip;
a second insulating layer disposed on the encapsulant;
a second redistribution layer comprising a signal line disposed on the encapsulant;
a first heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line; and
a surface treatment layer disposed on an exposed region of the second redistribution layer that is exposed from the second insulating layer,
wherein the first heat dissipation layer does not cover the surface treatment layer in a thickness direction.
2. The semiconductor package of claim 1 , wherein a portion of the second redistribution layer is disposed in a region in which the first heat dissipation layer and the semiconductor chip overlap in the thickness direction.
3. The semiconductor package of claim 1 , wherein the exposed region of the second redistribution layer has a plurality of patterns spaced apart from each other when viewed from above.
4. The semiconductor package of claim 1 , wherein the exposed region of the second redistribution layer is surrounded by the first heat dissipation layer when viewed from above.
5. The semiconductor package of claim 1 , wherein the first heat dissipation layer comprises a plurality of heat dissipation vias.
6. The semiconductor package of claim 1 , wherein the first heat dissipation layer has a plate shape.
7. The semiconductor package of claim 1 , wherein the second redistribution layer comprises a ground line, and
wherein the first heat dissipation layer is electrically connected to the ground line.
8. The semiconductor package of claim 7 , wherein the first heat dissipation layer and the ground line are connected to each other by a connection via penetrating through the second insulating layer.
9. The semiconductor package of claim 1 , further comprising a frame disposed on the connection structure and comprising a through-hole, in which the semiconductor chip is disposed.
10. The semiconductor package of claim 9 , wherein the frame comprises a wiring via connecting the first redistribution layer and second redistribution layer to each other.
11. The semiconductor package of claim 1 , wherein the second redistribution layer and the first heat dissipation layer are disposed in the second insulating layer.
12. The semiconductor package of claim 11 , wherein the first heat dissipation layer is embedded in the second insulating layer, and
wherein an upper surface of the heat dissipation layer is exposed from the second insulating layer.
13. The semiconductor package of claim 11 , wherein the first heat dissipation layer is disposed on the second redistribution layer.
14. The semiconductor package of claim 1 , further comprising a second heat dissipation layer disposed below the connection structure.
15. The semiconductor package of claim 14 , further comprising a passivation layer disposed below the connection structure and embedding the first redistribution layer,
wherein the second heat dissipation layer is embedded in the passivation layer, and
wherein a lower surface of the second heat dissipation layer is exposed from the passivation layer.
16. The semiconductor package of claim 15 , further comprising an underbump metal bump penetrating through the passivation layer and connected to the first redistribution layer of the connection structure.
17. The semiconductor package of claim 16 , wherein the underbump metal bump is surrounded by the second heat dissipation layer when viewed from below.
18. A semiconductor package comprising:
a semiconductor chip comprising connection pads;
a frame comprising a through-hole, in which the semiconductor chip is disposed;
an encapsulant covering portions of the semiconductor chip and the frame, and filling into portions of the through-hole;
a connection structure, on which the frame and the semiconductor chip are disposed, comprising first insulating layers and first redistribution layers alternately disposed, first connection vias respectively penetrating through the first insulating layers and connecting the first redistribution layers and the connection pads to each other;
a passivation layer disposed on a lowermost one of the first insulating layers, embedding a lowermost one of the first redistribution layers, and having openings exposing portions of the lowermost one of the first redistribution layers;
a second redistribution layer disposed on the encapsulant;
a second insulating layer disposed on the encapsulant and embedding the second redistribution layer; and
a heat dissipation layer embedded in at least one of the second insulating layer and the passivation layer, and having a first surface exposed from the at least one of the second insulating layer and the passivation layer,
wherein the heat dissipation layer has a second surface opposite to the first surface and side surfaces connecting the first surface and the second surface, and
wherein the second surface and the side surfaces are in contact with the at least one of the second insulating layer and the passivation layer.