Clock gate latency modeling based on analytical frameworks
View Patent ↗A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.
1. A method for modeling clock gate timing for an integrated circuit, the method comprising:
creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing;
applying an analytical framework to the dataset to determine coefficients based on the design features and measured values of clock gate timing;
measuring values of design features for a clock tree for the integrated circuit;
generating predicted values of clock gate timing for the clock tree for the integrated circuit based on the coefficients, wherein the predicted values of clock gate timing correspond to the measured values of the design features for the clock tree;
applying the predicted values of clock gate timing to a model of the clock tree for the integrated circuit; and
performing a synthesis of the clock tree for the integrated circuit based on the predicted values.
2. A method for modeling clock gate timing for an integrated circuit, the method comprising:
creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing;
applying an analytical framework to the dataset to determine coefficients based on the design features and measured values of clock gate timing;
measuring values of design features for a clock tree for the integrated circuit; and
generating predicted values of clock gate timing for the clock tree for the integrated circuit based on the coefficients;
wherein:
the clock tree for the integrated circuit is a second clock tree and part of a second build; and
creating the dataset comprises:
constructing a first clock tree as part of a first build,
measuring values of design features of the first clock tree, and
measuring corresponding values of clock gate timing of the first clock tree.
3. The method of claim 2 wherein the values of the design features and clock gate timing are measured after a physical synthesis of the first clock tree.
4. The method of claim 2 , further comprising applying the predicted values of clock gate timing to a model of the second clock tree.
5. The method of claim 4 , wherein the predicted values of clock gate timing are applied to the model of the second clock tree before a physical synthesis of the second clock tree.
6. The method of claim 1 , wherein the coefficients are determined for individual design features.
7. The method of claim 6 , wherein the coefficients are determined for combinations of design features.
8. The method of claim 7 , wherein different combinations of design features are used for different builds.
9. The method of claim 7 , wherein coefficients are determined for different permutations of the combinations of features.
10. The method of claim 9 , wherein different permutations of design features are used for different builds.
11. The method of claim 1 , wherein the analytical framework comprises machine learning.
12. The method of claim 11 , wherein the machine learning uses a neural network that is trained on the dataset.
13. The method of claim 1 , wherein the values of clock gate timing comprise latency values.
14. The method of claim 1 , wherein the clock tree for the integrated circuit comprises clock gate enable paths.
15. The method of claim 1 , further comprising applying one or more adjustments to the analytical framework.
16. A method for clock gate modeling for an integrated circuit, the method comprising:
constructing a first clock tree as part of a first build;
generating a first dataset by measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the clock gates of the first clock tree;
applying an analytical framework to the dataset to generate coefficients based on the measured values of the design features of the first clock tree and measured corresponding values of clock gate timing of the first clock tree;
measuring values of design features for a clock tree for the integrated circuit; and
generating predicted values of clock gate timing for the clock tree for the integrated circuit based on the coefficients and measured values of one or more corresponding design features used to generate the coefficients.
17. The method of claim 16 , further comprising iteratively applying the analytical framework to the first dataset to generate the coefficients.
18. A system for modeling clock gate timing for an integrated circuit, the system comprising:
an analytical platform configured to:
apply an analytical framework to a dataset having measured values of at least two design features and corresponding measured values of clock gate timing for a first clock tree build, wherein the analytical framework generates coefficients based on the design features and measured values of the clock gate timing; and
generate predicted values of clock gate timing for a second clock tree build based on the coefficients and measured values of one or more of the corresponding design features used to generate the coefficients.