Leadframe with die pad having cantilevers to secure electronic component

1. A leadframe, comprising:

a die pad having a plurality of sides which collectively define a rectangular die pad area including at least two securing sides, wherein the two securing sides each includes a linear portion with a cantilever interrupting the linear portion,

wherein the die pad has a top surface defining a top plane and a bottom surface defining a bottom plane;

lead terminals beyond the die pad;

wherein the cantilevers have a fixed end and a free end opposite the fixed end that enables flexing or bending responsive to a received force;

wherein the free ends include a distal end with an electronic component locking feature, and

wherein the fixed ends are positioned beyond the rectangular die pad area and the electronic component locking feature extends inward over the rectangular die pad area for providing mechanical support and for securing an electronic component.

2. The leadframe of claim 1 , wherein the electronic component locking feature includes a protruding sloped top portion and a lower portion indented relative to the top portion.

3. The leadframe of claim 1 , wherein the distal ends extend above the top plane a distance of 10 μm to 30 μm.

4. The leadframe of claim 2 , wherein the lower portion is planar and has a surface that is perpendicular to the top plane and to the bottom plane.

5. The leadframe of claim 1 , wherein the fixed ends are positioned beyond the rectangular die pad area by a distance of 1 mm to 3 mm, and wherein the electronic component locking feature extends inward over the rectangular die pad area by a distance of 0.1 mm to 1 mm.

6. The leadframe of claim 1 , wherein a width of the cantilever is at least 5% of a full width of the die pad.

7. A packaged semiconductor device, comprising:

a leadframe, comprising:

a die pad having a plurality of sides which collectively define a rectangular die pad area including at least two securing sides, wherein the two securing sides each includes a linear portion with a cantilever interrupting the linear portion,

wherein the die pad has a top surface defining a top plane and a bottom surface defining a bottom plane;

lead terminals beyond the die pad;

wherein the cantilevers have a fixed end and a free end opposite the fixed end that enables flexing or bending responsive to a received force;

wherein the free ends include a distal end with an electronic component locking feature;

wherein the fixed ends are positioned beyond the rectangular die pad area and the electronic component locking feature extends inward over the rectangular die pad area for providing mechanical support and for securing an electronic component, and

wherein the electronic component is on the die pad mechanically secured to the die pad by the cantilevers.

8. The packaged semiconductor device of claim 7 , wherein the electronic component comprises a laminate capacitor, laminate inductor, or a laminate transformer.

9. The packaged semiconductor device of claim 7 , wherein the electronic component comprises a semiconductor integrated circuit (IC) die.

10. The packaged semiconductor device of claim 7 , wherein the electronic component locking feature includes a protruding sloped top portion and a lower portion indented relative to the top portion.

11. The packaged semiconductor device of claim 10 , wherein the lower portion is planar and has a surface that is perpendicular to the top plane and to the bottom plane.

12. The packaged semiconductor device of claim 7 , wherein the fixed ends are positioned beyond the rectangular die pad area by a distance of 1 mm to 3 mm, and wherein the electronic component locking feature extends inward over the rectangular die pad area by a distance of 0.1 mm to 1 mm.

13. The packaged semiconductor device of claim 7 , wherein a width of the cantilever is at least 5% of a full width of the die pad.

14. A method forming a packaged semiconductor device, comprising:

providing a leadframe, comprising:

a die pad having a plurality of sides which collectively define a rectangular die pad area including at least two securing sides, wherein the two securing sides each includes a linear portion with a cantilever interrupting the linear portion,

wherein the die pad has a top surface defining a top plane and a bottom surface defining a bottom plane;

lead terminals beyond the die pad;

wherein the cantilevers have a fixed end and a free end opposite the fixed end that enables flexing or bending responsive to a received force;

wherein the free ends include a distal end with an electronic component locking feature, and

wherein the fixed ends are positioned beyond the rectangular die pad area and the electronic component locking feature extends inward over the rectangular die pad area for providing mechanical support and for securing an electronic component,

placing an electronic component having bond pads with its back side on the die pad, wherein the distal ends are pushed down by the electronic component to below the bottom plane, and then in response elastically move upwards to mechanically hold the electronic component from the two securing sides, and

wire bonding having bond pads to provide bond wires between the bond pads and the lead terminals.

15. The method of claim 14 , wherein the electronic component locking feature includes a protruding sloped top portion and a lower portion indented relative to the top portion, and wherein the elastically move upwards is so that the protruding sloped top portions act as a clip to mechanically hold the top side of the electronic component from the two securing sides.

16. The method of claim 14 , wherein the electronic component comprises a laminate inductor, a laminate transformer or a laminate capacitor.

17. The method of claim 14 , wherein the cantilevers are on each of the plurality of sides.

18. The method of claim 14 , wherein the free ends extend above the top plane a distance of 10 μm to 30 μm.

19. The method of claim 15 , wherein the lower portion is planar and has a surface that is perpendicular to the top plane and to the bottom plane.

20. The method of claim 14 , wherein the electronic component comprises a semiconductor integrated circuit (IC) die.

21. The method of claim 20 , wherein the semiconductor IC die comprises a silicon IC die, further comprising heating the silicon IC die to a temperature of at least 350° C. before the placing.