Apparatuses and methods for operations in a self-refresh state

1. An apparatus, comprising:

an array of memory cells coupled to sensing circuitry comprising a sense amplifier;

a controller configured to operate the array and sensing circuitry to perform compute operations; and

a mode register configured to:

provide a plurality of selectable modes, wherein the plurality of selectable modes includes:

a first mode in which compute operations are performed at a rate corresponding to a default frequency for a memory refresh cycle when the memory array is in a self-refresh state; and

a second mode in which no compute operations are performed when the memory array is in the self-refresh state; and

receive an indication to select from the plurality of modes when the array is in the self-refresh state.

2. The apparatus of claim 1 , wherein the sensing circuitry further comprises a compute component configured to perform logical operations on the data.

3. The apparatus of claim 1 , wherein the array is a dynamic random access memory (DRAM) array.

4. The apparatus of claim 1 , wherein the apparatus is a one bit vector processing apparatus.

5. The apparatus of claim 1 , wherein the plurality of selectable modes includes a third mode in which

the compute operations are performed at a rate different from the default frequency for the memory refresh cycle for the data stored in the memory cells; and

wherein the compute operations being performed at the rate different from the default frequency is based on adjustment of the memory refresh cycle frequency.

6. The apparatus of claim 1 , wherein:

the apparatus is a memory device comprising a plurality of banks, wherein each bank of the respective plurality of banks comprises:

an array of memory cells; and

a controller configured to operate the array and sensing circuitry to perform compute operations; and

the memory device further comprises the mode register being selectably coupled to each bank.

7. The apparatus of claim 6 , wherein a mode selected for a first bank is different from a mode selected for a second bank.

8. A method for operating a memory device, comprising:

providing, to a mode register, an indication to select from a plurality of modes for performance of compute operations on data stored in an array of memory cells when the array is in a self-refresh state, wherein the plurality of modes includes:

a first mode in which performance of the compute operations are performed at a rate corresponding to a default frequency for a memory refresh cycle for the data stored in the memory cells; and

a second mode in which performance of the compute operations are performed at a rate different from the default frequency for the memory refresh cycle for the data stored in the memory cells; and

setting a bit in microcode instructions stored in the mode register to enable the performance of the compute operations using a selected mode of the plurality of modes;

performing, the compute operations by a controller coupled to the array and configured to direct performance of the compute operations using sensing circuitry coupled to the array.

9. The method of claim 8 , wherein the method further comprises performing logical operations on the data using a compute component of the sensing circuitry.

10. The method of claim 8 , wherein

the plurality of selectable modes of the mode register includes a third mode in which compute operation are not performed when the array is

in the self-refresh state.

11. The method of claim 8 , wherein the method further comprises:

adjusting the memory refresh cycle frequency to enable the compute operations being performed at the rate different from the default frequency.

12. The method of claim 8 , wherein the method further comprises:

selectably coupling the mode register to each bank of a plurality of banks of the memory device, wherein each bank of the respective plurality of banks comprises:

an array of memory cells coupled to sensing circuitry comprising a sense amplifier; and

a controller configured to operate the array and sensing circuitry to perform compute operations; and

receiving, by the mode register, the indication to select from the plurality of modes a mode for a respective bank.

13. The method of claim 12 , wherein the method further comprises selecting a mode for a first bank that is different from a mode selected for a second bank.

14. An apparatus, comprising:

an array of memory cells coupled to sensing circuitry comprising a sense amplifier;

a controller configured to operate the array and sensing circuitry to perform compute operations; and

a mode register configured to:

provide a plurality of selectable modes, wherein the plurality of selectable modes includes:

a first mode in which compute operations are performed at a rate different than a default frequency for a memory refresh cycle when the memory array is in a self-refresh state; and

a second mode in which no compute operations are performed when the memory array is in the self-refresh state; and

receive an indication to select from the plurality of modes when the array is in the self-refresh state.