IP Library Granted Patent US 11,626,343
Granted Patent B2
US 11,626,343 · App. 16/665,783 · Granted Apr 11, 2023

Semiconductor device with enhanced thermal dissipation and method for making the same

Inventors: Yang-Che Chen (Hsinchu, TW); Chen-Hua Lin (Douliu, TW); Huang-Wen Tseng (Zhubei, TW); Victor Chiang Liang (Hsinchu, TW); Chwen-Ming Liu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L23/3736H01L23/3675H01L24/13H01L24/14H01L24/16H01L24/32H01L24/33H01L24/73H01L24/92H01L2224/13144H01L2224/13155H01L2224/14181H01L2224/14519H01L2224/16225H01L2224/16501H01L2224/32225H01L2224/32245H01L2224/32505H01L2224/33181H01L2224/33519H01L2224/73153H01L2224/73204H01L2224/73253H01L2224/83203H01L2224/83815H01L2224/92225
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Quick Facts
Patent No.
US 11,626,343
App. No.
16/665,783
Granted
Apr 11, 2023
Kind
B2
Abstract

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

Claims (46)

1. A method, comprising:

forming an integrated fan-out wafer on a frame, wherein the integrated fan-out wafer includes a plurality of chips disposed on a redistribution layer;

forming a metal pillar over a main surface of each of the plurality of chips;

forming a solder layer on each of the metal pillars;

separating the plurality of chips by a sawing operation after forming the solder layer;

bonding a lid to each of the plurality of chips via the solder layer after separating the plurality of chips;

applying heat and pressure to melt the solder layer and attach each lid to a corresponding chip via the solder layer and metal pillars; and

forming a thermal interface material layer between each of the metal pillars and between the main surface of the chip and the lid,

wherein the solder and thermal interface material are different materials, and

wherein the solder layer has a thermal conductivity of ≥50 W/mK.

2. The method according to claim 1 , further comprising forming a bonding pad on the main surface of each of the plurality of chips before forming the metal pillar.

3. The method according to claim 1 ,

wherein the solder layer comprises solder balls formed on each of the metal pillars.

4. The method according to claim 1 , wherein the metal pillars are formed of copper.

5. The method according to claim 1 , further comprising:

removing the plurality of chips from the frame; and

attaching the plurality of chips to a substrate,

wherein the removing and attaching the plurality of chips is performed before positioning the lids.

6. The method according to claim 5 , further comprising forming an underfill layer between the plurality of chips and the substrate.

7. The method according to claim 1 , wherein the heat and pressure are applied to each lid.

8. The method according to claim 7 , wherein a thermal compressive bond head is used to apply the heat and pressure to each lid.

9. A method, comprising:

forming an integrated fan-out wafer on a frame, wherein the integrated fan-out wafer includes a chip disposed on a redistribution layer;

forming a metal pillar on each of a plurality of bonding pads disposed on a main surface of the chip;

forming a solder layer on each of the metal pillars;

forming a thermal interface material layer between each of the metal pillars between the lid and the surface of the chip,

wherein the solder and thermal interface material are different materials;

positioning a lid over the solder layer on each of the metal pillars; and

applying heat and pressure to melt the solder layer and attach the lid to the chip via the solder layer.

10. The method according to claim 9 , wherein the solder layer comprises solder balls formed on each of the metal pillars.

11. The method according to claim 9 , wherein the metal pillars are formed of copper or nickel.

12. A method, comprising:

forming an integrated fan-out wafer on a frame, wherein the integrated fan-out wafer includes a chip disposed on a redistribution layer;

forming a solder bump comprising a solder on each of a plurality of bonding pads disposed on a main surface of the chip,

wherein the solder bumps are made of a tin-containing alloy and are spaced apart from each other;

positioning a lid over solder bumps formed on each of the plurality bonding pads;

applying heat and pressure to melt the solder bumps, causing the solder to flow, and adjacent spaced-apart solder bumps to merge with each other forming a solder layer; and

fixedly attaching the lid to the chip via the solder layer.

13. The method according to claim 12 , wherein the solder comprises a material having a thermal conductivity of ≥50 W/mK.

14. The method according to claim 9 , wherein the solder layer is made of a tin-containing alloy.

15. The method according to claim 1 , wherein the solder layer is made of a tin-containing alloy.

16. The method according to claim 9 , wherein a thermal compressive bond head is used to apply the heat and pressure to the lid.

17. The method according to claim 1 , wherein the solder layer is made of a tin-containing alloy.

18. The method according to claim 17 , wherein the thermal interface material is non-electrically conductive.

19. The method according to claim 17 , wherein the thermal interface material is a thermally conductive pad, phase change material, or ceramic-containing grease or paste.

20. The method according to claim 9 , wherein the thermal interface material is non-electrically conductive.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2020
From: CHEN, YANG-CHE; LIANG, VICTOR CHIANG; LIN, CHEN-HUA; LIU, CHWEN-MING; TSENG, HUANG-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052297/0834 →
Continuity (2)
Provisional Application 62753042 · Oct 30, 2018
Related Publication 20200135613A1 · Apr 30, 2020
Cited By (1)
US 12,283,535