Field-effect transistor with a heat absorber in contact with a surface of the gate electrode on its back side
A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.
1. A semiconductor device comprising:
a semiconductor substrate;
an insulator film covering a part of an upper surface of the semiconductor substrate;
a gate electrode opposing the upper surface of the semiconductor substrate via the insulator film;
an upper electrode being in contact with another part of the upper surface of the semiconductor substrate; and
a lower electrode being in contact with a lower surface of the semiconductor substrate,
wherein the semiconductor substrate comprises:
an n-type first semiconductor region being in contact with the upper electrode at the upper surface of the semiconductor substrate;
a p-type body layer located around the n-type first semiconductor region and opposing the gate electrode at the upper surface of the semiconductor substrate via the insulator film; and
an n-type drift layer located between the p-type body layer and the lower electrode and partly extending to the upper surface of the semiconductor substrate through the p-type body layer such that the n-type drift layer comprises an opposing surface that opposes the gate electrode via the insulator film at the upper surface of the semiconductor substrate,
wherein the insulator film extends from a lower surface of the gate electrode to an upper surface of the gate electrode by passing between the gate electrode and the upper electrode and defines an opening that exposes the upper surface of the gate electrode,
a side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that pass through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface, and
the semiconductor device further comprises a heat absorber being in contact with the upper surface of the gate electrode within the opening of the insulator film and having a greater thermal capacity per unit volume than the insulator film.
2. The semiconductor device according to claim 1 , wherein at least a part of the upper surface of the gate electrode that is located within the first region is in contact with the heat absorber.
3. The semiconductor device according to claim 1 , wherein the heat absorber is constituted of metal.
4. The semiconductor device according to claim 1 , wherein
the gate electrode is constituted of poly-silicon, and
the upper electrode is constituted of metal.
5. The semiconductor device according to claim 1 , wherein the insulator film is constituted of insulator that is inorganic material having covalent bonds.
6. The semiconductor device according to claim 5 , wherein the insulator constituting the insulator film is any one of silicon oxide, silicon nitride and aluminum nitride.
7. The semiconductor device according to claim 1 , wherein the semiconductor substrate further comprises an n-type drain layer, the n-type drain layer being located between the n-type drift layer and the lower electrode and being in contact with the lower electrode at the lower surface of the semiconductor substrate.
8. The semiconductor device according to claim 1 , wherein the semiconductor substrate further comprises a p-type collector layer, the p-type collector layer being located between the n-type drift layer and the lower electrode and being in contact with the lower electrode at the lower surface of the semiconductor substrate.