Semiconductor integrated circuit, electronic device and vehicle
A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region.
1. A semiconductor integrated circuit comprising:
an external terminal supplying a first power supply voltage;
a power supply circuit configured to generate a second power supply voltage greater than the first power supply voltage;
a semiconductor substrate; and
a first MOS transistor, a second MOS transistor and a P+ region that are provided on the semiconductor substrate, wherein
the first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which the first N-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which the third N-type region is electrically connected to the power supply circuit and is supplied with the second power supply voltage,
the P+ region is supplied with the first power supply voltage, and
in plan view of the semiconductor substrate,
the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and
the P+ region is located between the first N-type region and the third N-type region.
2. The semiconductor integrated circuit according to claim 1 , wherein
in plan view of the semiconductor substrate,
the fourth N-type region is located between the first N-type region and the third N-type region.
3. A semiconductor integrated circuit comprising:
an external terminal supplying a first power supply voltage;
a power supply circuit configured to generate a second power supply voltage greater than the first power supply voltage;
a semiconductor substrate; and
a first MOS transistor and a second MOS transistor that are provided on the semiconductor substrate, wherein
the first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which the first N-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which the third N-type region is electrically connected to the power supply circuit and is supplied with the second power supply voltage, and
in plan view of the semiconductor substrate,
the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and
the fourth N-type region is located between the first N-type region and the third N-type region.
4. The semiconductor integrated circuit according to claim 1 , wherein
the power supply circuit is configured to generate a third power supply voltage greater than the first power supply voltage,
the semiconductor integrated circuit further comprises a third MOS transistor and a fourth MOS transistor that are provided on the semiconductor substrate,
the third MOS transistor is an NMOS transistor which has a fifth N-type region and a sixth N-type region and in which the fifth N-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the fourth MOS transistor is an NMOS transistor which has a seventh N-type region and an eighth N-type region and in which the seventh N-type region is electrically connected to the power supply circuit and is supplied with the third power supply voltage, and
in plan view of the semiconductor substrate,
the first MOS transistor and the third MOS transistor are disposed to be adjacent to each other, and
the second MOS transistor and the fourth MOS transistor are disposed to be adjacent to each other, and
the first N-type region and the third N-type region are located between the fifth N-type region and the seventh N-type region.
5. A semiconductor integrated circuit comprising:
an external terminal supplying a first power supply voltage;
a power supply circuit configured to generate a second power supply voltage lesser than the first power supply voltage;
a semiconductor substrate; and
a first MOS transistor, a second MOS transistor and an N+ region that are provided on the semiconductor substrate wherein,
the first MOS transistor is a PMOS transistor which has a first P-type region and a second P-type region, and in which the first P-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the second MOS transistor is a PMOS transistor which has a third P-type region and a fourth P-type region and in which the third P-type region is electrically connected to the power supply circuit and is supplied with the second power supply voltage,
the N+ region is supplied with the first power supply voltage, and
in plan view of the semiconductor substrate,
the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and
the N+ region is located between the first P-type region and the third P-type region.
6. The semiconductor integrated circuit according to claim 5 , wherein
in plan view of the semiconductor substrate,
the fourth P-type region is located between the first P-type region and the third P-type region.
7. A semiconductor integrated circuit comprising:
an external terminal supplying a first power supply voltage;
a power supply circuit configured to generate a second power supply voltage lesser than the first power supply voltage;
a semiconductor substrate; and
a first MOS transistor and a second MOS transistor that are provided on the semiconductor substrate, wherein
the first MOS transistor is a PMOS transistor which has a first P-type region and a second P-type region, and in which the first P-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the second MOS transistor is a PMOS transistor which has a third P-type region and a fourth P-type region and in which the third P-type region is electrically connected to the power supply circuit and is supplied with the second power supply voltage,
in plan view of the semiconductor substrate,
the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and
the fourth P-type region is located between the first P-type region and the third P-type region.
8. The semiconductor integrated circuit according to claim 5 , wherein
the power supply circuit configured to generate a third power supply voltage lesser than the first power supply voltage,
the semiconductor integrated circuit further comprises a third MOS transistor and a fourth MOS transistor that are provided on the semiconductor substrate,
the third MOS transistor is a PMOS transistor which has a fifth P-type region and a sixth P-type region and in which the fifth P-type region is electrically connected to the external terminal and is supplied with the first power supply voltage,
the fourth MOS transistor is a PMOS transistor which has a seventh P-type region and an eighth P-type region and in which the seventh P-type region is electrically connected to the power supply circuit and is supplied with the third power supply voltage,
in plan view of the semiconductor substrate,
the first MOS transistor and the third MOS transistor are disposed to be adjacent to each other, and
the second MOS transistor and the fourth MOS transistor are disposed to be adjacent to each other, and
the first P-type region and the third P-type region are located between the fifth P-type region and the seventh P-type region.
9. The semiconductor integrated circuit according to claim 1 , further comprising:
a fifth MOS transistor; and
a sixth MOS transistor; wherein
an inverter circuit includes the first MOS transistor and the fifth MOS transistor, and
an analog switch circuit includes the second MOS transistor and the sixth MOS transistor.
10. An electronic device comprising the semiconductor integrated circuit according to claim 1 .
11. A vehicle comprising the semiconductor integrated circuit according to claim 1 .