Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same

1. A semiconductor device, comprising:

a first semiconductor structure comprising a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts;

a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts; and

a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface,

wherein the first semiconductor structure further comprises a peripheral circuit comprising an input/output buffer, a decoder, and a sense amplifier configured to facilitate operations of the array of DRAM cells in the second semiconductor structure; and

each DRAM cell comprises a selection transistor and a capacitor, and the capacitor is disposed below the selection transistor.

2. The semiconductor device of claim 1 , wherein the first semiconductor structure comprises:

a substrate;

the processor on the substrate;

the array of SRAM cells on the substrate and outside of the processor; and

the first bonding layer above the processor and the array of SRAM cells.

3. The semiconductor device of claim 2 , wherein the second semiconductor structure comprises:

the second bonding layer above the first bonding layer;

the array of DRAM cells above the second bonding layer; and

a semiconductor layer above and in contact with the array of DRAM cells.

4. The semiconductor device of claim 3 , further comprising a pad-out interconnect layer above the semiconductor layer.

5. The semiconductor device of claim 1 , wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the processor, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells; and

the processor and the array of SRAM cells are electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

6. The semiconductor device of claim 1 , wherein the array of SRAM cells are distributed in a plurality of separate regions in the first semiconductor structure.

7. The semiconductor device of claim 3 , wherein the semiconductor layer comprises single-crystal silicon.

8. The semiconductor device of claim 1 , wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the processor, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells.

9. The semiconductor device of claim 8 , wherein the processor is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

10. The semiconductor device of claim 8 , wherein the array of SRAM cells are electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

11. A semiconductor device, comprising:

a first semiconductor structure comprising a processor, an array of static random-access memory (SRAM) cells, and a peripheral circuit;

a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells; and

a bonding interface jointing the first semiconductor structure and the second semiconductor structure,

wherein the peripheral circuit in the first semiconductor structure comprises an input/output buffer, a decoder, and a sense amplifier, and is configured to facilitate operations of the array of DRAM cells in the second semiconductor structure; and

each DRAM cell comprises a selection transistor and a capacitor, and the capacitor is disposed below the selection transistor.

12. The semiconductor device of claim 11 , wherein the first semiconductor structure further comprises a first bonding layer comprising a plurality of first bonding contacts in contact with the bonding interface.

13. The semiconductor device of claim 11 , wherein the second semiconductor structure further comprises a second bonding layer comprising a plurality of second bonding contacts in contact with the bonding interface.

14. The semiconductor device of claim 11 , wherein the first semiconductor structure comprises:

a substrate;

the processor on the substrate;

the array of SRAM cells on the substrate and outside of the processor; and

a first bonding layer above the processor and the array of SRAM cells.

15. The semiconductor device of claim 14 , wherein the second semiconductor structure comprises:

a second bonding layer above the first bonding layer;

the array of DRAM cells above the second bonding layer; and

a semiconductor layer above and in contact with the array of DRAM cells.

16. The semiconductor device of claim 15 , wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the processor, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells.

17. The semiconductor device of claim 16 , wherein the processor is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

18. The semiconductor device of claim 16 , wherein the array of SRAM cells are electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

19. The semiconductor device of claim 11 , wherein the array of SRAM cells are distributed in a plurality of separate regions in the first semiconductor structure.