Ferroelectric memory device
A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
1. A semiconductor memory device comprising:
a stacked body in which conductive layers are stacked in a first direction;
a semiconductor layer provided in the stacked body and extending in the first direction;
a first insulating layer provided between the conductive layers and the semiconductor layer, the first insulating layer containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric;
a second insulating layer provided between the first insulating layer and the semiconductor layer, the second insulating layer having a chemical composition different from a chemical composition of the first insulating layer; and
a third insulating layer provided between the second insulating layer and the semiconductor layer, the third insulating layer containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric.
2. The semiconductor memory device according to claim 1 , further comprising
a fourth insulating layer provided between the third insulating layer and the semiconductor layer, the fourth insulating layer having a chemical composition different from a chemical composition of the third insulating layer.
3. The semiconductor memory device according to claim 1 , wherein
the semiconductor layer is polycrystalline silicon.
4. The semiconductor memory device according to claim 1 , wherein
the first insulating layer and the third insulating layer contain hafnium oxide.