Instruction address based data prediction and prefetching

1. A method comprising:

receiving a first instruction for execution by a processor;

accessing, by a load address predictor (LAP), a LAP table entry for a section of an instruction cache, wherein the section of the instruction cache comprises a plurality of instructions that includes the first instruction, the section having an associated section address in the LAP table;

predicting, by the LAP and using the LAP table entry, a set of data addresses that will be loaded;

sending, to a load-store unit (LSU), a recommendation to prefetch the set of data addresses;

storing, using a circular FIFO flush buffer, information for every instruction cache section that hits the LAP table;

flushing, in response to performing a pipeline flush, the LAP table entry; and

restoring the values in the LAP table entry using the flush buffer.

2. The method of claim 1 , wherein the recommendation sent to the LSU includes a confidence score that indicates a probability that the set of data addresses will be loaded during execution of a program that includes the first instruction.

3. The method of claim 2 , wherein the LSU is configured to prefetch the set of data addresses in response to the confidence score exceeding a predetermined threshold.

4. The method of claim 1 , the method further comprising:

updating, by the LAP and at completion, the LAP table entry.

5. The method of claim 4 , wherein updating the LAP table entry includes coalescing, by the LAP, multiple loads of an unrolled loop to the same line into a single entry.

6. The method of claim 1 , wherein the LAP table entry includes:

a first value for the number of times the section has been seen at instruction fetch;

a second value for the number of times the section has been reported at completion;

a third value for the number of iterations of the section before moving to the next line in a data cache;

a fourth value of the number of iterations of the section seen in a given pass; and

a fifth value indicating a confidence level of the recommendation.

7. The method of claim 6 , wherein the third value is determined based on historical access patterns for instruction addresses.

8. A system comprising a processor configured to perform a method comprising:

receiving a first instruction for execution by the processor;

determining that the first instruction is in a section of an instruction cache, wherein the section comprises a plurality of instructions;

accessing, in response to determining that the first instruction is in the section, by a load address predictor (LAP), a LAP table entry for the section of the instruction cache;

predicting, by the LAP and using the LAP table entry, a set of data addresses that will be loaded;

sending, to a load-store unit (LSU), a recommendation to prefetch the set of data addresses;

storing, using a circular FIFO flush buffer, information for every instruction cache section that hits the LAP table;

flushing, in response to performing a pipeline flush, the LAP table entry; and

restoring the values in the LAP table entry using the flush buffer.

9. The system of claim 8 , wherein the recommendation sent to the LSU includes a confidence score that indicates a probability that the set of data addresses will be loaded during execution of a program that includes the first instruction, wherein the set of data addresses includes at least two data addresses, and wherein the LSU is configured to prefetch the set of data addresses in response to the confidence score exceeding a predetermined threshold.

10. The system of claim 8 , wherein the method further comprises:

updating, by the LAP and at completion, the LAP table entry, wherein updating the LAP table entry includes coalescing, by the LAP, multiple loads of an unrolled loop to the same line into a single entry.

11. The system of claim 8 , wherein the LAP table entry includes:

a first value for the number of times the section has been seen at instruction fetch; and

a second value indicating a confidence level of the recommendation.

12. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processor to cause the processor to perform a method comprising:

receiving a first instruction for execution by the processor;

determining that the first instruction is in a section of an instruction cache, wherein the section comprises a plurality of instructions and has an associated section identifier;

accessing, by a load address predictor (LAP), a LAP table entry for the section of the instruction cache using the section identifier, wherein the LAP table entry includes a first value for the number of times the section has been seen at instruction fetch, a second value for the number of iterations of the section before moving to the next line in a data cache, and a third value indicating a confidence level of the recommendation;

predicting, by the LAP and using the LAP table entry, a set of data addresses that will be loaded; and

sending, to a load-store unit (LSU), a recommendation to prefetch the set of data addresses.

13. The computer program product of claim 12 , wherein the recommendation sent to the LSU includes a confidence score that indicates a probability that the set of data addresses will be loaded during execution of a program that includes the first instruction, and wherein the LSU is configured to prefetch the set of data addresses in response to the confidence score exceeding a predetermined threshold.

14. The computer program product of claim 12 , wherein the method further comprises:

updating, by the LAP and at completion, the LAP table entry, wherein updating the LAP table entry includes coalescing, by the LAP, multiple loads of an unrolled loop to the same line into a single entry.

15. The method of claim 1 , the method further comprising:

determining, by the LAP, that a prefetch trigger is met,

wherein the predicting the set of data addresses that will be loaded is performed in response to determining that the prefetch trigger is met.

16. The method of claim 1 , wherein the section of the instruction cache comprises a plurality of cache lines.

17. The method of claim 1 , the method further comprising:

determining, using an instruction address of the first instruction, the section of the instruction cache that includes the first instruction.

18. The method of claim 17 , wherein accessing the LAP table entry for the section of the instruction cache comprises:

determining a section address for the section that includes the first instruction; and

accessing the LAP table entry for the section in the LAP using the section address.