IP Library › Granted Patent US 11,817,422
Granted Patent B2
US 11,817,422 · App. 16/679,180 · Granted Nov 14, 2023

Semiconductor device

Inventor: Yohei Igarashi (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L25/0652H01L23/36H01L23/4334H01L23/49811H01L24/13H01L24/16H01L24/32H01L24/81H01L24/97H01L25/18H01L25/50H01L25/071H01L28/10H01L2224/16238H01L2225/06503H01L2225/06513H01L2225/06517H01L2225/06531H01L2225/06555H01L2225/06589
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Quick Facts
Patent No.
US 11,817,422
App. No.
16/679,180
Granted
Nov 14, 2023
Kind
B2
Abstract

A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.

Claims (24)

1. A semiconductor device, comprising:

a first semiconductor element;

a first connection terminal formed on a lower surface of the first semiconductor element;

a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view;

a second connection terminal formed on a lower surface of the second semiconductor element;

a wiring substrate including a first connection pad electrically connected to the first connection terminal and a second connection pad electrically connected to the second connection terminal, wherein the first semiconductor element and the second semiconductor element are mounted over the wiring substrate;

a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal;

a heat dissipation plate mounted on an upper surface of the first semiconductor element;

a spacer formed on a lower surface of the heat dissipation plate, wherein the second semiconductor element is mounted on a lower surface of the spacer; and

an underfill resin with which a gap between the heat dissipation plate and the wiring substrate is filled to encapsulate the first semiconductor element and the second semiconductor element, wherein

the first connection terminal is a metal post,

the third connection terminal is a core solder ball,

the core solder ball includes a spherical core ball and solder covering a periphery of the core ball,

the metal post is electrically connected to the core solder ball via a first solder layer,

a side surface of the spacer is separated from a side surface of the heat dissipation plate toward an inner side of the semiconductor device,

a side surface of the second semiconductor element is separated from the side surface of the spacer further toward the inner side of the semiconductor device,

the side surface and the lower surface of the heat dissipation plate, the side surface and the lower surface of the spacer, and the side surface and the lower surface of the second semiconductor element are formed in a stepped manner

the lower surface of the spacer is coplanar with the lower surface of the first semiconductor element, and

the second semiconductor element is bonded to the lower surface of the spacer and the lower surface of the first semiconductor element.

2. The semiconductor device according to claim 1 , wherein a stacked structure of the metal post and the core solder ball is connected between the first semiconductor element and the wiring substrate; and the core solder ball has a diameter that is greater than a height of the metal post.

3. The semiconductor device according to claim 1 , wherein the second connection terminal is a metal post; and the core solder ball has a diameter that is greater than a height of the metal post of the second connection terminal.

4. The semiconductor device according to claim 1 , wherein the first semiconductor element includes a first coil, the second semiconductor element includes a second coil that differs from the first coil, and the first coil of the first semiconductor element is magnetically coupled to the second coil of the second semiconductor element.

5. The semiconductor device according to claim 1 , wherein the second connection terminal is electrically connected to the second connection pad via a second solder layer that differs from the first solder layer.

6. The semiconductor device according to claim 1 , wherein the first solder layer includes a portion extending outside the core solder ball in a plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2019
From: IGARASHI, YOHEI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 050963/0465 →
Priority Claims (1)
JP 2018-212921 · Nov 13, 2018 · national
Continuity (1)
Related Publication 20200152601A1 · May 14, 2020
Cited By (1)
US 12,512,390