Time-driven placement and/or cloning of components for an integrated circuit

1. A system, comprising:

a memory that stores computer executable components;

a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:

a geometric area component that determines a plurality of geometric areas of an integrated circuit based on timing information and distance information between a set of transistor components of the integrated circuit; and

a placement component that:

determines a location for a latch component on the integrated circuit that improves at least one power characteristic of the integrated circuit based on an intersection between the plurality of geometric areas of the integrated circuit, and

presents an integrated circuit layout with the latch component at the location on the integrated circuit.

2. The system of claim 1 , further comprising an analysis component that determines a slack timing value between the set of transistor components that satisfies a defined criterion, and wherein the geometric area component determines the plurality of geometric areas of the integrated circuit based on the slack timing value.

3. The system of claim 1 , wherein the latch component is a first latch component and the location is a first location on the integrated circuit, wherein the computer executable components further comprise a cloning component that clones the first latch component to generate a second latch component, and wherein the cloning component determines a second location for a second latch component on the integrated circuit based on the intersection between the plurality of geometric areas.

4. The system of claim 3 , wherein the cloning component determines a first set of transistor components associated with the first latch component and a second set of transistor components associated with the second latch component based on the intersection between the plurality of geometric areas.

5. The system of claim 1 , wherein the geometric area component determines a total number of geometric areas of the integrated circuit based on the timing information and the distance information.

6. The system of claim 1 , wherein a first geometric area of the plurality of geometric areas comprises a first portion of transistors from the set of transistor components and a second geometric area of the plurality of geometric areas comprises a second portion of transistors from the set of transistor components.

7. The system of claim 1 , wherein the location for the latch component facilitates optimized power characteristics for the integrated circuit.

8. A computer-implemented method, comprising:

determining, by a system operatively coupled to a processor, a plurality of geometric areas of an integrated circuit based on timing information and distance information between a set of transistor components of the integrated circuit;

determining, by the system, a location for a sequencing element on the integrated circuit that improves at least one power characteristic of the integrated circuit based on an intersection between the plurality of geometric areas of the integrated circuit; and

presenting, by the system, an integrated circuit layout with the sequencing element at the location on the integrated circuit.

9. The computer-implemented method of claim 8 , further comprising:

determining, by the system, a slack timing value between the set of transistors that satisfies a defined criterion, wherein the determining the plurality of geometric areas comprises determining the plurality of geometric areas based on the slack timing value.

10. The computer-implemented method of claim 8 , wherein the sequencing element is a first sequencing element and the location is a first location on the integrated circuit, the computer-implemented method further comprising:

cloning, by the system, the sequencing element to generate a second sequencing element; and

determining, by the system, a second location for a second sequencing element on the integrated circuit based on the intersection between the plurality of geometric areas.

11. The computer-implemented method of claim 10 , further comprising:

determining, by the system, a first set of transistors for the first sequencing element based on the intersection between the plurality of geometric areas; and

determining, by the system, a second set of transistors associated with the second sequencing element based on the intersection between the plurality of geometric areas.

12. The computer-implemented method of claim 8 , wherein the determining the location for the sequencing element comprises determining the location for the sequencing element between a first transistor and a second transistor from the set of transistors based on the intersection between the plurality of geometric areas.

13. The computer-implemented method of claim 8 , wherein the location for the sequencing element facilitates optimized power characteristics for the integrated circuit.

14. A computer program product for improving design of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processor to cause the processor to:

determine, by the processor, a plurality of geometric areas of the integrated circuit based on timing information and distance information associated with a set of transistors of the integrated circuit;

determine, by the processor, a location for a sequencing element on the integrated circuit that improves at least one power characteristic of the integrated circuit based on an intersection between the plurality of geometric areas of the integrated circuit; and

presenting, by the processor, an integrated circuit layout with the sequencing element at the location on the integrated circuit.

15. The computer program product of claim 14 , wherein the program instructions are further executable by the processor to cause the processor to:

determine, by the processor, a slack timing value between the set of transistors that satisfies a defined criterion; and

determine, by the processor, the plurality of geometric areas of the integrated circuit based on the slack timing value.

16. The computer program product of claim 14 , wherein the sequencing element is a first sequencing element and the location is a first location on the integrated circuit, and wherein the program instructions are further executable by the processor to cause the processor to:

duplicate, by the processor, the first sequencing element to generate a second sequencing element; and

determine, by the processor, a second location for a second sequencing element on the integrated circuit based on the intersection between the plurality of geometric areas.

17. The computer program product of claim 16 , wherein the program instructions are further executable by the processor to cause the processor to:

determine, by the processor, a first set of transistors for the first sequencing element based on the intersection between the first geometric area and the second geometric area; and

determine, by the processor, a second set of transistors associated with the second sequencing element based on the intersection between the plurality of geometric areas.

18. The computer program product of claim 14 , wherein the program instructions are further executable by the processor to cause the processor to:

determine, by the processor, the location for the sequencing element between a first transistor and a second transistor from the set of transistors based on the intersection between the plurality of geometric areas.

19. The computer program product of claim 14 , wherein a first geometric area of the plurality of geometric areas comprises a first portion of transistors from the set of transistor components and a second geometric area of the plurality of geometric areas comprises a second portion of transistors from the set of transistor components.

20. The computer program product of claim 14 , wherein the location for the sequencing element facilitates optimized power characteristics for the integrated circuit.