Digital clock generation with randomized division of a source clock

1. A circuit for use in generating a digital clock for a digital clock domain interfaced to another clock domain through a FIFO (first in first out) component, based on randomized division of a source clock, the circuit comprising:

division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division value; and

division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on:

the input randomizing sequence of clock division factors, and an accumulated drift correction signal; and

a clock drift control loop to generate the accumulated drift correction signal, based at least in part on an accumulated clock drift value relative to the target average clock division value.

2. The circuit of claim 1 , further comprising a clock generator circuit, including the circuit, to generate the digital clock from the source clock based on randomized division with the drift-corrected randomizing sequence of clock division factors.

3. The circuit of claim 1 , wherein the FIFO component is configured with a defined FIFO depth, and wherein the drift-corrected randomizing sequence of clock division factors is generated so that clock drift is bounded based on the defined FIFO depth.

4. The circuit of claim 1 , wherein the input randomizing sequence of clock division factors is generated with a linear feedback shift register.

5. The circuit of claim 4 , wherein:

the division arbitration circuitry generates each drift-corrected clock division factor of the drift-corrected randomizing sequence of clock division factors from a valid subset of the randomizing sequence of clock division factors determined based at least in part on the accumulated drift correction signal;

the drift-corrected clock division factor selected from the valid subset of the randomizing sequence of clock division factors based on a second linear feedback shift register.

6. The circuit of claim 1 , wherein the clock drift control loop includes:

clock drift accumulator circuitry to accumulate clock drift relative to the target division value using first and second clock-drift thresholds associated with respective first and second threshold subsets of the defined set of clock division factors; and

drift correction circuitry to generate the accumulated drift correction signal based on the accumulated clock drift relative to the first and second clock-drift thresholds.

7. The circuit of claim 2 , wherein:

the randomized division of the source clock is fractional based at least in part on a probability mapping of the input randomized sequence of clock division factors, and the target average division value.

8. The circuit of claim 2 , wherein:

the clock generator circuit to generate the digital clock from the source clock using clock phasing;

during each clock phase, the clock generator circuit to perform randomized division with the drift-corrected randomizing sequence of clock division factors.

9. The circuit of claim 1 , for use in a radio frequency communications device that is one of a receiver device or a transmitter device, wherein the device includes:

an analog signal chain in an analog clock domain, and a digital signal chain in a digital clock domain;

an interface between the analog clock domain and the digital clock domain, the interface including the FIFO component; and

a digital clock generator including the circuit, to generate the digital clock from the source clock based on randomized division with the drift-corrected randomizing sequence of clock division factors.

10. A radio frequency communications device, comprising:

an analog signal chain in an analog clock domain, and a digital signal chain in a digital clock domain;

an interface circuit between the analog clock domain and the digital clock domain, the interface including a FIFO component; and

a digital clock generator circuit to generate the digital clock from a source clock, the digital clock generator circuit including:

division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division value, and

division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on:

the input randomizing sequence of clock division factors, and an accumulated drift correction signal; and

a clock drift control loop to generate the accumulated drift correction signal, based at least in part on an accumulated clock drift value relative to the target average clock division value.

the digital clock generator circuit to generate the digital clock from the source clock based on randomized division with the drift-corrected randomizing sequence of clock division factors.

11. The device of claim 10 , wherein the FIFO component is configured with a defined FIFO depth, and wherein the drift-corrected randomizing sequence of clock division factors is generated so that clock drift is bounded based on the defined FIFO depth.

12. The device of claim 10 , wherein the input randomizing sequence of clock division factors is generated with a linear feedback shift register.

13. The device of claim 12 , wherein:

the division arbitration circuitry generates each drift-corrected clock division factor of the drift-corrected randomizing sequence of clock division factors from a valid subset of the randomizing sequence of clock division factors determined based at least in part on the accumulated drift correction signal;

the drift-corrected clock division factor selected from the valid subset of the randomizing sequence of clock division factors based on a second linear feedback shift register.

14. The circuit of claim 10 , wherein the clock drift control loop includes:

clock drift accumulator circuitry to accumulate clock drift relative to the target division value using first and second clock-drift thresholds associated with respective first and second threshold subsets of the defined set of clock division factors; and

drift correction circuitry to generate the accumulated drift correction signal based on the accumulated clock drift relative to the first and second clock-drift thresholds.

15. The device of claim 10 , wherein:

the randomized division of the source clock is fractional based at least in part on a probability mapping of the input randomized sequence of clock division factors, and the target average division value.

16. The device of claim 10 , wherein:

the clock generator circuit to generate the digital clock from the source clock using clock phasing;

during each clock phase, the clock generator circuit to perform randomized division with the drift-corrected randomizing sequence of clock division factors.

17. The device of claim 10 , wherein the device is one of a radio frequency transmitter or a radio frequency receiver.

18. A method of generating a digital clock for a digital clock domain interfaced to another clock domain through a FIFO (first in first out) component, based on randomized division of a source clock, the method comprising:

generating an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division value;

generating an accumulated drift correction signal, based at least in part on an accumulated clock drift value relative to the target average clock division value; and

generating a drift-corrected randomizing sequence of clock division factors, based at least in part on:

the input randomizing sequence of clock division factors, and

the accumulated drift correction signal.

generating the digital clock from the source clock based on randomized division with the drift-corrected randomizing sequence of clock division factors.

19. The method of claim 18 , wherein the FIFO component is configured with a defined FIFO depth, and wherein the drift-corrected randomizing sequence of clock division factors is generated so that clock drift is bounded based on the defined FIFO depth.

20. The method of claim 18 , further comprising:

generating the input randomizing sequence of clock division factors based on a first linear feedback shift register; and

generating each drift-corrected clock division factor of the drift-corrected randomizing sequence of clock division factors from a valid subset of the randomizing sequence of clock division factors determined based at least in part on the accumulated drift correction signal;

the drift-corrected clock division factors selected from the valid subset of the randomizing sequence of clock division factors based on a second linear feedback shift register.

21. The method of claim 18 , wherein generating the accumulated drift correction signal includes:

accumulating a clock drift relative to the target division value using first and second clock-drift thresholds associated with respective first and second threshold subsets of the defined set of clock division factors; and

generating the accumulated drift correction signal based on the accumulated clock drift relative to the first and second clock-drift thresholds.

22. The method of claim 18 , further comprising:

generating the digital clock from the source clock using clock phasing; and

during each clock phase, performing randomized division with the drift-corrected randomizing sequence of clock division factors.

23. The method of claim 18 , for use in a radio frequency communications device that is one of a receiver device or a transmitter device, wherein the device includes:

an analog signal chain in an analog clock domain, and a digital signal chain in a digital clock domain; and

an interface between the analog clock domain and the digital clock domain, the interface including the FIFO component.