Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t 1 . An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.
1. A method for controlling a neuromorphic memory system, the neuromorphic memory system including a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell, the method comprising:
generating a presynaptic leaky integrate and fire (LIF) pulse on a presynaptic LIF line at time t 1 ;
activating an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse, the access transistor enabling LIF current to pass through the resistive memory cell to a postsynaptic LIF line;
integrating the LIF current at the postsynaptic LIF line over time;
comparing a LIF voltage at the postsynaptic LIF line to a threshold voltage;
generating a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line at time t 2 if the LIF voltage is beyond the threshold voltage; and
programming the resistive memory cell to a resistance proportional to a time difference between generating the postsynaptic STDP pulse and generating the presynaptic LIF pulse (t 2 −t 1 ).
2. The method of claim 1 , wherein integrating the LIF current is performed by a LIF capacitor electrically coupled to the postsynaptic LIF line.
3. The method of claim 2 , further comprising discharging the LIF capacitor over time.
4. The method of claim 1 , further comprising:
wherein comparing the LIF voltage to the threshold voltage is performed by a LIF comparator configured to compare the LIF voltage to the threshold voltage; and
wherein generating the postsynaptic STDP pulse is performed by the LIF comparator configured to generate the postsynaptic STDP pulse if the LIF voltage is beyond the threshold voltage.
5. The method of claim 1 , wherein the postsynaptic STDP pulse provides a STDP current through the resistive memory cell to program the resistive memory cell to the resistance proportional to t 2 −t 1 .
6. The method of claim 5 , further comprising:
generating a presynaptic STDP pulse at a presynaptic STDP line, the presynaptic STDP pulse characterized by f VD1 −1 (h(Δt)), where h is a target STDP behavior function describing a desired relative change in synaptic weight of the resistive memory cell based on a time difference Δt between when the postsynaptic STDP pulse is generated at t 2 and when the presynaptic LIF pulse is generated at t 1 , and f VD1 is a memory cell characteristic function describing a relationship between change in an electrical resistance of the memory cell and a voltage of the presynaptic STDP pulse at a voltage of the postsynaptic STDP pulse;
activating a program transistor coupled to the presynaptic STDP line in response to the presynaptic STDP pulse, the access transistor enabling the STDP current to pass through the resistive memory cell.