Litho-etch-litho-etch with self-aligned blocks

1. A method for fabricating a semiconductor device including self-aligned vias and self-aligned blocks, comprising:

forming a plurality of mandrel cuts in a first set of patterned mandrels of a base structure using lithography;

surrounding the first set of patterned mandrels and a second set of patterned mandrels of the base structure with spacer material to form mandrel-spacer structures;

forming a flowable material layer on exposed surfaces of the mandrel-spacer structures; and

performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

2. The method of claim 1 , further comprising patterning a plurality of mandrels including the first and second sets of patterned mandrels from mandrel material of the base structure.

3. The method of claim 1 , wherein forming the plurality of mandrel cuts further includes performing a partial organic planarization layer (OPL) etch.

4. The method of claim 1 , wherein the base structure further includes:

a substrate;

at least one dielectric sublayer formed on the substrate; and

a hardmask layer, wherein the plurality of mandrels are formed on the hardmask layer.

5. The method of claim 4 , wherein surrounding the first and second sets of mandrels with spacer material further includes depositing the spacer material on the hardmask layer.

6. The method of claim 4 , wherein performing the additional processing further includes:

transferring non-mandrel shape patterns into the flowable material layer;

forming non-mandrel cut patterns in the flowable material layer;

etching back the spacer material to expose surfaces of the plurality of mandrels;

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer to form a final pattern including remaining portions of the spacer material;

etching the hardmask layer using the final pattern;

removing the remaining portions of the spacer material; and

forming the plurality of dielectric trenches.

7. The method of claim 6 , further comprising performing a metallization process based on the additional processing, including removing the hardmask layer, forming conductive material, and planarizing the conductive material.

8. The method of claim 6 , wherein performing the additional processing further includes performing a via double patterning process prior to forming the non-mandrel cut patterns.

9. The method of claim 8 , wherein performing the via double patterning process further includes:

forming non-mandrel vias using lithography based on an organic planarization layer (OPL);

forming mandrel vias using lithography; and

forming first and second trenches.

10. The method of claim 9 , wherein:

forming first trenches further includes etching the plurality of mandrels, the hardmask layer and the at least one dielectric sublayer; and

forming the second trenches further includes:

removing the OPL and coating a protective OPL layer into the non-mandrel and mandrel vias;

etching back to reveal the plurality of mandrels and the flowable material layer; and

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer.

11. A method for fabricating a semiconductor device including self-aligned vias and self-aligned blocks, comprising:

patterning a plurality of mandrels including a first set of mandrels and a second set of mandrels from mandrel material of a base structure;

forming a plurality of mandrel cuts in the first set of mandrels using lithography, including performing a partial organic planarization layer (OPL) etch;

surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures;

forming a flowable material layer on exposed surfaces of the mandrel-spacer structures; and

performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

12. The method of claim 11 , wherein the base structure further includes:

a substrate;

at least one dielectric sublayer formed on the substrate; and

a hardmask layer, wherein the plurality of mandrels are formed on the hardmask layer.

13. The method of claim 12 , wherein surrounding the first and second sets of mandrels with spacer material further includes depositing the spacer material on the hardmask layer.

14. The method of claim 12 , wherein performing the additional processing further includes:

transferring non-mandrel shape patterns into the flowable material layer;

forming non-mandrel cut patterns in the flowable material layer;

etching back the spacer material to expose surfaces of the plurality of mandrels;

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer to form a final pattern including remaining portions of the spacer material;

etching the hardmask layer using the final pattern;

removing the remaining portions of the spacer material; and

forming the plurality of dielectric trenches.

15. The method of claim 14 , further comprising performing a metallization process, including removing the hardmask layer, forming conductive material, and planarizing the conductive material.

16. The method of claim 14 , wherein performing the additional process further includes performing a via double patterning process prior to forming the non-mandrel cut patterns.

17. The method of claim 16 , wherein performing the via double patterning process further includes:

forming non-mandrel vias using lithography based on an organic planarization layer (OPL);

forming mandrel vias using lithography; and

forming first and second trenches.

18. The method of claim 17 , wherein:

forming first trenches further includes etching the plurality of mandrels, the hardmask layer and the at least one dielectric sublayer; and

forming the second trenches further includes:

removing the OPL and coating a protective OPL layer into the non-mandrel and mandrel vias;

etching back to reveal the plurality of mandrels and the flowable material layer; and

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer.

19. A method for fabricating a semiconductor device including self-aligned vias and self-aligned blocks, comprising:

forming, on a hardmask layer of a base structure, a plurality of mandrels including a first set of mandrels and a second set of mandrels from mandrel material of a base structure, the base structure further including a substrate and at least one dielectric sublayer formed on the substrate;

forming a plurality of mandrel cuts from the first set of mandrels using lithography, including performing a partial organic planarization layer (OPL) etch;

surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, including depositing the spacer material on the hardmask layer;

forming a flowable material layer on exposed surfaces of the mandrel-spacer structures;

performing additional processing, including:

transferring non-mandrel shape patterns into the flowable material layer;

forming non-mandrel cut patterns in the flowable material layer;

etching back the spacer material to expose surfaces of the plurality of mandrels;

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer to form a final pattern including remaining portions of the spacer material;

etching the hardmask layer using the final pattern;

removing the remaining portions of the spacer material; and

forming a plurality of dielectric trenches within the base structure based on the patterns; and

performing a metallization process, including removing the hardmask layer, forming conductive material and planarizing the conductive material.

20. The method of claim 19 , wherein performing the additional process further includes performing a via double patterning process prior to forming the non-mandrel cut patterns, including:

forming non-mandrel vias using lithography based on an organic planarization layer (OPL) by etching the plurality of mandrels, the hardmask layer and the at least one dielectric sublayer;

forming mandrel vias using lithography, including:

removing the OPL and coating a protective OPL layer into the non-mandrel and mandrel vias;

etching back to reveal the plurality of mandrels and the flowable material layer; and

selectively removing mandrel and non-mandrel materials including the plurality of mandrels and the flowable material layer; and

forming first and second trenches.