Vertical memory devices with high density dummy channel structure
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors. The semiconductor device also includes a first dummy channel structure that is disposed through a first stair region of the stair-step form, a second dummy channel structure that is disposed through a second stair region of the stair-step form adjacent to the first stair region, and a third dummy channel structure that is disposed at a boundary between the first stair region and the second stair region.
1. A semiconductor device, comprising:
a substrate;
a plurality of gate layers and a plurality of insulating layers that are stacked alternately over a first region of the substrate, the plurality of gate layers and the plurality of insulating layers being stacked of a stair-step form over a second region of the substrate;
a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers, and the channel structure and the plurality of gate layers forming a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors;
a first dummy channel structure that is disposed through a first stair region of the stair-step form;
a first contact structure that is disposed over the first stair region;
a second dummy channel structure that is disposed through a second stair region of the stair-step form, the second stair region being immediately next to the first stair region in a cross section of the semiconductor device;
a second contact structure that is disposed over the second stair region; and
a third dummy channel structure that is disposed at a boundary between the first stair region and the second stair region,
wherein the first dummy channel structure, the second dummy channel structure, the third dummy channel structure, the first contact structure, and the second contact structure are disposed along a common line in a planar view of the semiconductor device and the first dummy channel structure, the second dummy channel structure, and the third dummy channel structure are disposed between the first contact structure and the second contact structure, the second contact structure being a contact structure that is immediately adjacent to the first contact structure along the common line in the planar view of the semiconductor.
2. The semiconductor device of claim 1 , further comprising:
a fourth dummy channel structure that is disposed through the first stair region of the stair-step form; and
a fifth dummy channel structure that is disposed through the second stair region of the stair-step form, wherein
the first dummy channel structure and the fourth dummy channel structure are disposed in a first row,
the second dummy channel structure and the fifth dummy channel structure are disposed in a second row, and
the third dummy channel structure is disposed between the first row and the second row.
3. The semiconductor device of claim 1 , wherein
the first contact structure is disposed over the first stair region at a distance from the third dummy channel structure that is greater than a distance between the first dummy channel structure and the first contact structure, and
the second contact structure is disposed over the second stair region at a distance from the third dummy channel structure that is greater than a distance between the second dummy channel structure and the second contact structure.
4. The semiconductor device of claim 1 , wherein the first contact structure and the second contact structure are conductively connected to a first gate layer and a second gate layer in the plurality of gate layers, respectively.
5. The semiconductor device of claim 1 , wherein a minimum distance between each dummy channel structure and each contact structure is greater than or equal to a first limit.
6. The semiconductor device of claim 1 , wherein a maximum distance between two neighboring dummy channel structures is less than or equal to a second limit.
7. The semiconductor device of claim 1 , wherein the channel structure and the third dummy channel structure are formed of a same material.
8. The semiconductor device of claim 1 , wherein the third dummy channel structure has a circular shape.
9. The semiconductor device of claim 1 , wherein the third dummy channel structure is disposed between the first dummy channel structure and the second dummy channel structure.
10. The semiconductor device of claim 1 , wherein the first dummy channel structure is neighboring to the first contact structure and the second dummy channel structure is neighboring to the second contact structure.