Use of a single instruction set architecture (ISA) instruction for vector normalization
Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.
1. A method comprising:
responsive to receipt by a graphics processing unit (GPU) of a single instruction specifying a vector normalization operation to be performed on each vector of a set of V vectors:
generating, by a first processing unit of the GPU, V squared length values, each representing a squared length of one of the set of V vectors, N squared length values at a time, by, for each N sets of inputs, each representing a plurality of component vectors for N of the set of V vectors and stored in respective registers of a first set of V/N registers, performing N parallel dot product operations on the N sets of inputs, wherein V and N are integers >0 and V >N; and
generating, by a second processing unit of the GPU, V sets of outputs, each representing a plurality of normalized component vectors of one of the set of V vectors, N sets of outputs at a time, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.
2. The method of claim 1 , wherein said generating, by a second processing unit of the GPU, V sets of outputs stores the V sets of outputs, N sets of outputs at a time, in respective registers of a second set of V/N registers.
3. The method of claim 2 , wherein V is eight and wherein N is two.
4. The method of claim 3 , wherein the first set of V/N registers comprises four 256-bit registers, and wherein the plurality of component vectors comprises three 32-bit component vectors.
5. The method of claim 4 , wherein the second set of V/N registers comprises four 256-bit registers, and wherein the plurality of normalized component vectors comprises three 32-bit normalized component vectors.
6. The method of claim 3 , wherein the first processing unit comprises a floating point unit (FPU) and wherein the second processing unit comprises a co-processor.
7. The method of claim 3 , wherein the N parallel dot product operations result from a 2-wide Single Instruction Multiple Data (SIMD) dot product instruction.
8. The method of claim 3 , wherein the N parallel operations result from a 2-wide Single Instruction Multiple Data (SIMD) instruction.
9. The method of claim 1 , wherein the reciprocal square root function comprises performing a single-precision reciprocal square root operation on an operand, including:
performing a reciprocal square root operation on an exponent component of the operand;
performing a reciprocal square root operation on a mantissa component of the operand, comprising:
dividing the mantissa component into a first sub-component and a second sub-component;
determining a result of the reciprocal square root operation for the first sub-component; and
determining a result of the reciprocal square root operation for the second sub-component; and
returning a result of the reciprocal square root operation.
10. A graphics processing unit (GPU) comprising:
a first set of V/N registers, wherein V and N are integers >0 and V >N;
a first processing unit coupled to the first set of V/N registers;
a second processing unit coupled to the first set of V/N registers;
an execution unit operable to, responsive to receipt of a single instruction specifying a vector normalization operation to be performed on each vector of a set of V vectors, (i) issue V/N N-wide Single Instruction Multiple Data (SIMD) dot product operations to be performed by the first processing unit; and (ii) issue V/N N-wide Single Instruction Multiple Data (SIMD) operations that implement a combination of a reciprocal square root function and a vector scaling function to be performed by the second processing unit;
wherein the first processing unit is operable to generate V squared length values, each representing a squared length of one of the set of V vectors, N squared length values at a time, by, for each N sets of inputs, each representing a plurality of component vectors for N of the set of V vectors and stored in respective registers of the first set of V/N registers, executing one of the V/N N-wide SIMD dot product operations; and
wherein the second processing unit is operable to generate V sets of outputs, each representing a plurality of normalized component vectors of one of the set of V vectors, N sets of outputs at a time, by for each N squared length values of the V squared length values, executing one of the V/N N-wide SIMD operations.
11. The GPU of claim 10 , further comprising a first set of V/N registers and wherein the V sets of outputs are stored, N sets of outputs at a time, in respective registers of the second set of V/N registers.
12. The GPU of claim 11 , wherein V is eight and wherein N is two.
13. The GPU of claim 12 , wherein the first set of V/N registers comprises four 256-bit registers, and wherein the plurality of component vectors comprises three 32-bit component vectors.
14. The GPU of claim 13 , wherein the second set of V/N registers comprises four 256-bit registers, and wherein the plurality of normalized component vectors comprises three 32-bit normalized component vectors.
15. The GPU of claim 12 , wherein the first processing unit comprises a floating point unit (FPU) and wherein the second processing unit comprises a co-processor.
16. The GPU of claim 10 , wherein the reciprocal square root function comprises performing a single-precision reciprocal square root operation on an operand, including:
performing a reciprocal square root operation on an exponent component of the operand;
performing a reciprocal square root operation on a mantissa component of the operand, comprising:
dividing the mantissa component into a first sub-component and a second sub-component;
determining a result of the reciprocal square root operation for the first sub-component; and
determining a result of the reciprocal square root operation for the second sub-component; and
returning a result of reciprocal square root operation.
17. The GPU of claim 16 , wherein determining the value of the first sub-component comprises determining an initial estimate for the first sub-component and determining a difference between an actual value of the first sub-component and the initial estimate for the first sub-component.
18. The GPU of claim 17 , wherein determining the initial estimate comprises performing a linear interpolation.
19. The GPU of claim 18 , wherein the difference between the actual value of the first sub-component and the initial estimate for the first sub-component is determined via a piecewise linear approximation.
20. The GPU of claim 16 , wherein determining the result of the reciprocal square root operation for the first and second sub-components is performed in parallel.