Cryogenic refrigeration for low temperature devices

1. A method for fabricating an active cooling structure, comprising:

forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-superconducting layer and a superconducting layer, wherein:

the non-superconducting layer comprises a plurality of generally parallel non-superconducting traces running in a first direction between first common pads; and

the superconductor layer comprises a plurality of generally parallel superconducting traces running in a second direction between second common pads.

2. The fabrication method of claim 1 , wherein:

the plurality of NIS structures are formed in a grid pattern at intersections of the plurality of generally parallel non-superconducting traces and the plurality of generally parallel superconducting traces;

the first common pads electrically connect the plurality of superconducting traces in parallel; and

the second common pads electrically connect the non-superconducting traces in parallel.

3. The fabrication method of claim 2 , further comprising:

applying a photoresist layer to a substrate;

exposing the photoresist layer in a pattern to create exposed photoresist and unexposed photoresist;

removing the exposed photoresist layer;

applying the metal layer onto the unexposed photoresist and the substrate; and

removing the unexposed photoresist.

4. The fabrication method of claim 3 , further comprising forming an insulator layer on the non-superconducting layer.

5. The fabrication method of claim 4 further comprising:

applying a lift-off resist layer to the insulator layer;

exposing the lift-off resist layer in a pattern to create exposed lift-off resist and unexposed lift-off resist;

removing the exposed lift-off resist layer;

applying the superconducting layer onto the unexposed lift-off resist layer and the insulator layer; and

removing the unexposed lift-off resist.

6. The fabrication method of claim 5 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises silicon dioxide; and

the superconductor layer comprises aluminum.

7. The fabrication method of claim 5 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises silicon dioxide; and

the superconductor layer comprises niobium.

8. The fabrication method of claim 5 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises hafnium dioxide; and

the superconductor layer comprises aluminum.

9. The fabrication method of claim 5 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises hafnium dioxide; and

the superconductor layer comprises niobium.

10. A fabrication method for a quantum processor, comprising:

forming a plurality of qubits formed on the first substrate; and

forming an active cooling structure in thermal communication with the qubits, the active cooling structure comprising an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-superconducting layer and a superconducting layer, wherein:

the non-superconducting layer comprises a plurality of generally parallel non-superconducting traces running in a first direction between first common pads;

the superconductor layer comprises a plurality of generally parallel superconducting traces running in a second direction between second common pads;

an insulator layer is formed on top of the non-superconducting layer; and

the superconductor layer is formed on top of the insulator layer.

11. The fabrication method of claim 10 , further comprising:

applying a photoresist layer to a substrate;

exposing the photoresist layer in a pattern to create exposed photoresist and unexposed photoresist;

removing the exposed photoresist layer;

applying the metal layer onto the unexposed photoresist and the substrate; and

removing the unexposed photoresist.

12. The fabrication method of claim 11 , further comprising forming an insulator layer on the non-superconducting layer.

13. The fabrication method of claim 12 , further comprising:

applying a lift-off resist layer to the insulator layer;

exposing the lift-off resist layer in a pattern to create exposed lift-off resist and unexposed lift-off resist;

removing the exposed lift-off resist layer;

applying the superconducting layer onto the unexposed lift-off resist layer and the insulator layer; and

removing the unexposed lift-off resist.

14. The fabrication method of claim 13 , wherein:

the non-superconducting layer comprises silver;

the insulator layer is chosen from the group consisting of silicon dioxide and hafnium dioxide; and

the superconductor layer is chosen from the group consisting of aluminum and niobium.

15. The fabrication method of claim 14 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises silicon dioxide; and

the superconductor layer comprises aluminum.

16. The fabrication method of claim 14 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises silicon dioxide; and

the superconductor layer comprises niobium.

17. The fabrication method of claim 14 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises hafnium dioxide; and

the superconductor layer comprises aluminum.

18. The fabrication method of claim 14 , wherein:

the non-superconducting layer comprises silver;

the insulator layer comprises hafnium dioxide; and

the superconductor layer comprises niobium.

19. The fabrication method of claim 10 , wherein:

the plurality of superconducting traces and the plurality of non-superconducting traces intersect at a plurality of locations in the X-Y plane; and

the plurality of NIS structures are formed in a grid pattern at the intersections.

20. A semiconductor fabrication system for fabricating a thermalization structure, the semiconductor fabrication system comprising:

a computer readable storage media having a set of instructions for a fabrication facility encoded thereon which, when operated by a processor causes a fabrication method to be performed, the fabrication method comprising:

forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer, wherein:

the non-superconducting layer comprises a plurality of generally parallel non-superconducting traces running in a first direction between first common pads; and

the superconductor layer comprises a plurality of generally parallel superconducting traces running in a second direction between second common pads.