Nanosheet transistors with different gate dielectrics and workfunction metals
Methods of forming semiconductor devices include patterning a stack of layers that includes channel layers, n-type doped first sacrificial layers between the channel layers, and carbon-doped second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers and the second sacrificial layers are recessed relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers. Inner spacers are formed in recesses formed by the recessing of the first sacrificial layers and the second sacrificial layers. The first sacrificial layers and the second sacrificial layers are etched away to leave the channel layers suspended.
1. A method for forming a semiconductor device, comprising:
patterning a stack of layers that includes channel layers, n-type doped first sacrificial layers having a first thickness between the channel layers, and carbon-doped second sacrificial layers having a second thickness between the channel layers and the first sacrificial layers, to form one or more device regions, wherein the second thickness is less than a dislocation thickness to cause dislocations between the second sacrificial layers and the channel layers, and wherein a combination of the first thickness and the second thickness is greater than the dislocation thickness;
recessing the first sacrificial layers and the second sacrificial layers relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers;
forming inner spacers in recesses formed by the recessing of the first sacrificial layers and the second sacrificial layers; and
etching away the first sacrificial layers and the second sacrificial layers to leave the channel layers suspended.
2. The method of claim 1 , wherein the channel layers are formed from crystalline silicon, the first sacrificial layers are formed from doped silicon, and the second sacrificial layers comprise silicon germanium.
3. The method of claim 2 , wherein recessing the first sacrificial layers comprises a chlorine gas etch at a partial pressure of about 0.17 Torr in a temperature range between 25° C. and 90° C. and wherein recessing the second sacrificial layers comprises a wet etch selected from the group consisting of a hydrogen peroxide and hydrofluoric acid etch, a nitric acid and hydrofluoric acid etch, and an ammonium hydroxide and hydrogen peroxide etch.
4. The method of claim 1 , wherein the first sacrificial layers and the second sacrificial layers are each etched away in a respective etch, wherein each respective etch selectively removes a respective sacrificial material without damaging the channel layers.
5. The method of claim 1 , further comprising forming the stack of layers by epitaxially growing the channel layers, the first sacrificial layers, and the second sacrificial layers in a repeating ABAC pattern.
6. The method of claim 5 , wherein A layers represent the second sacrificial layers, B layers represent the first sacrificial layers, and C layers represent the channel layers.
7. The method of claim 1 , wherein the second sacrificial layers comprise silicon germanium and wherein a thickness of the second sacrificial layers is less than about 8 nm.
8. The method of claim 1 , wherein the one or more device regions comprise an n-type device region and a p-type device region.
9. The method of claim 8 , further comprising forming a gate stack in at least one of the n-type region and the p-type region, including forming a dual layer of workfunction metals.
10. The method of claim 1 , further comprising depositing a gate stack, including forming an oxide dielectric layer on the suspended channel layers of at least one device region.
11. The method of claim 10 , wherein the oxide dielectric layer has a thickness between about 2 nm and about 5 nm.
12. A method for forming a semiconductor device, comprising:
patterning a stack of layers that includes silicon channel layers, sacrificial n-type doped silicon layers having a first thickness between the channel layers, and sacrificial carbon-doped silicon germanium diffusion barrier layers having a second thickness between the silicon channel layers and the sacrificial doped silicon layers, to form one or more device regions, wherein the second thickness is less than a dislocation thickness to cause dislocations between the sacrificial carbon-doped silicon germanium diffusion barrier layers and the channel layers, and wherein a combination of the first thickness and the second thickness is greater than the dislocation thickness;
recessing the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium diffusion barrier layers relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the sacrificial n-type doped silicon layers and respective sacrificial carbon-doped silicon germanium diffusion barrier layers;
forming inner spacers, in recesses formed by the recessing of the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers, that have flat, vertical sidewalls facing the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers;
etching away the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers to leave the channel layers suspended.
13. The method of claim 12 , wherein the sacrificial doped silicon layers and the sacrificial silicon germanium layers are each etched away in a respective etch, wherein each respective etch selectively removes a respective sacrificial material without damaging the channel layers.
14. The method of claim 12 , further comprising forming the stack of layers by epitaxially growing the silicon channel layers, the sacrificial doped silicon layers, and the sacrificial silicon germanium layers in a repeating ABAC pattern.
15. The method of claim 14 , wherein A layers represent the sacrificial silicon germanium layers, B layers represent the sacrificial doped silicon layers, and C layers represent the silicon channel layers.
16. The method of claim 12 , wherein a thickness of the sacrificial silicon germanium layers is less than about 8 nm.
17. The method of claim 12 , wherein the one or more device regions comprise an n-type device region and a p-type device region.
18. The method of claim 17 , further comprising forming a gate stack in at least one of the n-type region and the p-type region, including forming a dual layer of workfunction metals.
19. The method of claim 12 , wherein recessing the sacrificial n-type doped silicon layers comprises a chlorine gas etch at a partial pressure of about 0.17 Torr in a temperature range between 25° C. and 90° C. and wherein recessing the sacrificial carbon-doped silicon germanium diffusion barrier layers comprises a wet etch selected from the group consisting of a hydrogen peroxide and hydrofluoric acid etch, a nitric acid and hydrofluoric acid etch, and an ammonium hydroxide and hydrogen peroxide etch.
20. The method of claim 1 , further comprising forming the stack of layers by epitaxial growth of the channel layers, the first sacrificial layers, and the second sacrificial layers.