Bit matrix multiplication
Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.
1. An apparatus comprising:
a decoder to decode a single instruction have fields for an opcode, an identifier of a first source bit matrix location, an identifier of a second source bit matrix location, an identifier of a destination bit matrix location, and operation selection information to dictate a type of bit matrix multiplication and a type of accumulation; and
execution circuitry to execute the decoded instruction according to the opcode to perform the dictated type of bit matrix multiplication and type of accumulation of a first source bit matrix of the identified first source bit matrix location with a second source bit matrix of the identified second source bit matrix location, and store a result of the bit matrix multiplication and accumulation into the identified destination bit matrix location.
2. The apparatus of claim 1 , wherein the operation selection information is an immediate of the instruction.
3. The apparatus of claim 2 , wherein four bits of the immediate are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.
4. The apparatus of claim 2 , wherein four bits of the immediate are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.
5. The apparatus of claim 1 , wherein the first source matrix is an 8×8 bit matrix and the second source bit matrix is an 8×64 bit matrix.
6. The apparatus of claim 1 , wherein the first source matrix is an 64×8 bit matrix and the second source bit matrix is an 8×8 bit matrix.
7. The apparatus of claim 1 , wherein the first source matrix is an 8×64 bit matrix and the second source bit matrix is an 64×64 bit matrix.
8. The apparatus of claim 1 , wherein the second source bit matrix is stored in memory.
9. The apparatus of claim 1 , wherein the first source matrix is an 64×8 bit matrix and the identified second source bit matrix is an 64×8 bit matrix.
10. The apparatus of claim 1 , wherein the first source bit matrix is stored in memory.
11. The apparatus of claim 1 , wherein the bit matrix multiplication, comprises: for each bit position in the identified destination bit matrix location, a multiplication of a value from each bit position of a corresponding row in the first source bit matrix by a value of corresponding S-bit position of a corresponding column in the second source bit matrix, an accumulate each of the multiplications, and store of a result of the accumulate.
12. The apparatus of claim 1 , further comprising:
non-volatile memory to store one of the first and second source bit matrices.
13. The apparatus of claim 1 , wherein the decoder is further to translate the single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture to be decoded.
14. A method comprising:
decoding a single instruction have fields for an opcode, an identifier of a first source bit matrix location, an identifier of a second source bit matrix location, an identifier of a destination bit matrix location, and operation selection information to dictate a type of bit matrix multiplication and a type of accumulation; and
executing the decoded single instruction according to the opcode to perform the dictated type of bit matrix multiplication and type of accumulation of a first source bit matrix of the identified first source bit matrix location with a second source bit matrix of the identified second source bit matrix location, and store a result of the bit matrix multiplication and accumulation into the identified destination bit matrix location.
15. The method of claim 14 , wherein the operation selection information is an immediate of the instruction.
16. The method of claim 15 , wherein four bits of the immediate are used to select the accumulation operation of the group of exclusive OR (XOR), AND, OR, and NOR.
17. The method of claim 15 , wherein four bits of the immediate are used to select the multiplication operation of the group of exclusive OR (XOR), AND, OR, and NOR.
18. The method of claim 14 , wherein the first source matrix is an 8×8 bit matrix and the second source bit matrix is an 8×64 bit matrix.
19. The method of claim 14 , wherein the first source matrix is an 64×8 bit matrix and the second source bit matrix is an 8×8 bit matrix.
20. The method of claim 14 , wherein the first source matrix is an 8×64 bit matrix and the second source bit matrix is an 64×64 bit matrix.
21. The method of claim 14 , wherein the second source bit matrix is stored in memory.
22. The method of claim 14 , wherein the first source matrix is an 64×8 bit matrix and the identified second source bit matrix is an 64×8 bit matrix.
23. The method of claim 14 , wherein the first source bit matrix is stored in memory.
24. The method of claim 14 , wherein the bit matrix multiplication, comprises: for each bit position in the identified destination bit matrix location, a multiplication of a value from each bit position of a corresponding row in the first source bit matrix by a value of corresponding S-bit position of a corresponding column in the second source bit matrix, an accumulate each of the multiplications, and store of a result of the accumulate.