Semiconductor memory device applying different voltages to respective select gate lines

1. A semiconductor memory device comprising:

a memory string including first and second select transistors and memory cell transistors which are serially connected in this order;

a bit line connected to the first select transistor;

word lines which are connected to gates of the memory cell transistors, respectively, and which are stacked via insulating layers;

first and second select gate lines which are connected to gates of the first and second select transistors, respectively, and which are stacked on the word lines via insulating layers;

a first contact plug connected to the first select gate line;

a second contact plug connected to the second select gate line;

a first wiring layer provided on the first and second contact plugs; and

a row decoder connected to the first wiring layer,

wherein the row decoder applies the same voltage to the first and second select gate lines,

the first and second select gate lines are electrically isolated from one another at a second end opposite, across the memory string, to a first end on a side where the row decoder is disposed,

at a first time, the row decoder applies a first voltage to the first and second select gate lines, and applies a second voltage to the word lines,

at a second time, the row decoder applies a ground voltage to the first and second select gate lines and the word lines, and

at a third time, the row decoder applies a third voltage to the word lines.

2. The device according to claim 1 , further comprising:

a third select transistor connected between the second select transistor and the word lines;

a third select gate line which is connected to a gate of the third select transistor and which is provided between the word lines and the second select gate line via an insulating layer; and

a third contact plug connected to the third select gate line and the first wiring layer,

wherein the row decoder applies the same voltage to the first to third select gate lines, and

the first to third select gate lines are electrically isolated from one another at the second end.

3. The device according to claim 1 , further comprising:

a third select transistor connected between the second select transistor and the word lines;

a third select gate line which is connected to a gate of the third select transistor and which is provided between the word lines and the second select gate line via an insulating layer;

a third contact plug connected to the first end of the third select gate line and the first wiring layer,

a fourth contact plug connected to the second end of the first select gate line;

a fifth contact plug connected to the second end of the second select gate line; and

a second wiring layer provided on the fourth and fifth contact plugs,

wherein the row decoder applies the same voltage to the first to third select gate lines.

4. The device according to claim 1 , wherein

at a fourth time, the row decoder applies a write voltage higher than the third voltage to a selected word line.

5. The device according to claim 1 , wherein

the second voltage is equal to or lower than the third voltage.

6. The device according to claim 3 , wherein

the third select gate line is electrically isolated from the first and second select gate lines at the second end.

7. The device according to claim 1 , wherein

the first voltage is a voltage which brings the first and second select transistors into an on-state, and

the second voltage is a voltage which brings the memory cell transistors into an on-state regardless of threshold voltages of the memory cell transistors.