Method of manufacturing semiconductor devices and semiconductor devices

1. A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material;

forming a first barrier layer on the gate dielectric layer;

forming a second barrier layer on an upper surface of the first barrier layer;

forming a first work function adjustment layer on the second barrier layer;

removing the first work function adjustment layer and the second barrier layer;

after the first work function adjustment layer and the second barrier layer are removed, at least partially removing the first barrier layer;

after the first barrier layer is at least partially removed, forming a second work function adjustment layer over the gate dielectric layer; and

forming a metal gate electrode layer over the second work function adjustment layer.

2. The method of claim 1 , wherein the first barrier layer is made of TiN or TiN doped with Si and the second barrier layer is made of TaN.

3. The method of claim 1 , wherein:

the first work function adjustment layer is made of TiN, and

the second work function adjustment layer is made of one selected from the group consisting of TiAl, TiAlC, TaAl, TaAlC and TiAlN.

4. The method of claim 2 , wherein the first work function adjustment layer and the second barrier layer are removed together by a wet etching operation.

5. The method of claim 4 , wherein an etchant of the wet etching operation includes at least one selected from the group consisting of NH 4 OH, H 2 O 2 and HCl.

6. The method of claim 2 , wherein:

the first work function adjustment layer is removed by a first etching operation and the second barrier layer is removed by a second etching operation using a different etchant than the first etching operation,

the first etching operation is a wet etching using a first etchant and the second etching operation is a wet etching using a second etchant,

the first and second etchants include at least one selected from the group consisting of NH 4 OH, H 2 O 2 and HCl, and

the first etchant is different from the second etchant.

7. The method of claim 2 , wherein:

the first work function adjustment layer is removed by a first etching operation and the second barrier layer is removed by a second etching operation using a different etchant than the first etching operation,

the first etching operation is a wet etching using a first etchant and the second etching operation is a dry etching using a second etchant,

the first etchant include at least one selected from the group consisting of NH 4 OH, H 2 O 2 and HCl, and

the second etchant includes a gas containing at least one selected from the group consisting of WCl x and HCl.

8. The method of claim 1 , wherein:

the second work function adjustment layer is formed on the first barrier layer.

9. The method of claim 1 , wherein:

after the first work function adjustment layer and the second barrier layer are removed, the first barrier layer is fully removed, and

the second work function adjustment layer is formed on the gate dielectric layer.

10. A method of manufacturing a semiconductor device including a first n-type field effect transistor (NFET) and a second NFET, the method comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material of each of a first NFET region and a second NFET region;

forming a first barrier layer on the gate dielectric layer;

forming a second barrier layer on the first barrier layer;

forming a first work function adjustment layer on the second barrier layer;

removing the first work function adjustment layer and the second barrier layer from the first NFET region, while the first work function adjustment layer and the second barrier layer are maintained in the second NFET region;

after the first work function adjustment layer and the second barrier layer are removed from the first NFET region, forming a second work function adjustment layer in the first and second NFET regions; and

forming a metal gate electrode layer over the second work function adjustment layer.

11. The method of claim 10 , wherein the first barrier layer is made of TiN or TiN doped with Si and the second barrier layer is made of TaN.

12. The method of claim 10 , wherein:

the first work function adjustment layer is made of TiN, and

the second work function adjustment layer is made of one selected from the group consisting of TiAl, TiAlC, TaAl, TalC and TiAlN.

13. The method of claim 11 , wherein the first work function adjustment layer and the second barrier layer are removed in the first NFET region together by a wet etching operation.

14. The method of claim 11 , wherein the first work function adjustment layer is removed by a first wet etching operation and the second barrier layer is removed by a second wet etching operation using a different etchant than the first wet etching operation, in the first NFET region.

15. The method of claim 10 , wherein:

after the first work function adjustment layer and the second barrier layer are removed in the first NFET region, a part of the first barrier layer is removed,

the second work function adjustment layer is formed on the first barrier layer in the first NFET region, and

a thickness of the first barrier layer in the first NFET region is smaller than a thickness of the first barrier layer in the second NFET region.

16. The method of claim 10 , further comprising, after the first work function adjustment layer and the second barrier layer are removed in the first NFET region, removing the first barrier layer in the first NFET region,

wherein the second work function adjustment layer is formed on the gate dielectric layer in the first NFET region.

17. The method of claim 10 , wherein, when the first work function adjustment layer and the second barrier layer are removed from the first NFET region, the second NFET region is covered by one or more organic layers.

18. A method of manufacturing a semiconductor device including a first n-type field effect transistor (NFET), a second NFET and a third NFET, the method comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material of each of a first NFET region, a second NFET region and a third NFET region;

forming a first barrier layer on the gate dielectric layer;

forming a second barrier layer on the first barrier layer;

forming a first work function adjustment layer on the second barrier layer;

forming a second work function adjustment layer on the first work function adjustment layer;

removing the second work function adjustment layer from the first and second NFET regions and maintaining the second work function adjustment layer in the third NFET region;

removing the first work function adjustment layer and the second barrier layer from the first NFET region;

after the first work function adjustment layer and the second barrier layer are removed from the first NFET region, forming a third work function adjustment layer in the first, second and third NFET regions; and

forming a metal gate electrode layer over the third work function adjustment layer.

19. The method of claim 18 , wherein:

the first work function adjustment layer is removed by a first wet etching operation using a first etchant in the first NFET region, while the second and third NFET regions are covered by one or more organic layers, and

the second barrier layer is removed in the first NFET region by a second wet etching operation using a second etchant different from the first etchant, and the second and third NFET regions are exposed to the second etchant.

20. The method of claim 18 , wherein:

the first work function adjustment layer is removed by a dry etching operation in the first NFET region, while the second and third NFET regions are covered by one or more organic layers, and

the second barrier layer is removed in the first NFET region by a wet etching operation using an aqueous etchant, and the second and third NFET regions are exposed to the aqueous etchant.