Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range

1. A systolic multiply accumulate processor logically organized in rows and columns, each row comprising:

one or more normalizers, the one or more normalizers comprising a normalizer configured to convert a 16-bit input data element into a normalized 18-bit input data element, each of the one or more normalizers comprising:

a denormal detector configured to detect that the 16-bit input data element is in a denormal form;

a shifter configured to shift a significand of the 16-bit input data element based at least in part on the denormal detector detecting the denormal form;

an exponent expander configured to increase a quantity of bits representing an exponent portion of the 16-bit input data element; and

a subtractor configured to adjust a value of the exponent portion based at least in part on a shift of the significand; and

a plurality of processing elements configured to sequentially receive the normalized 18-bit input data element from the one or more normalizers, each processing element in the plurality of processing elements comprising:

a first input port for receiving the normalized 18-bit input data element;

a second input port for receiving a normalized weight;

a weight register for storing the normalized weight;

a third input port for receiving an input partial sum;

a multiplier configured to multiply the normalized 18-bit input data element by the normalized weight to generate a multiplier product; and

an adder configured to generate a 34-bit addition result by adding the multiplier product and the input partial sum.

2. The systolic multiply accumulate processor of claim 1 , wherein:

each of the one or more normalizers is configured to convert the 16-bit input data element into a first normalized 18-bit input data element when an input data element has a floating-point 16-bit (FP16) format;

each of the one or more normalizers is configured to convert the 16-bit input data element into a second normalized 18-bit input data element format when the input data element has a brain floating-point 16-bit (BF16) format;

the first normalized 18-bit input data element and the second normalized 18-bit input data element have different exponent lengths; and

the first normalized 18-bit input data element and the second normalized 18-bit input data element have different significand lengths.

3. The systolic multiply accumulate processor of claim 2 , further comprising:

the multiplier is comprised of two or more multiplier data paths, wherein:

a first multiplier data path is comprised of a 1-bit sign data path, a 10-bit significand data path, and a 7-bit exponent data path; and

a second multiplier data path is comprised of a 1-bit sign data path, a 7-bit significand data path, and a 10-bit exponent data path;

a controller is configured to select among two or more multiplier data paths based at least in part upon a data type control signal; and

the adder is a 34-bit floating-point adder, wherein the adder is comprised of, a 1-bit sign, a 23-bit significand, and a 10-bit exponent.

4. The systolic multiply accumulate processor of claim 1 , wherein each of the one or more normalizers is configured to convert a 16-bit input data element into a normalized 18-bit input data element and each of the one or more normalizers is further configured to convert a 16-bit weight into a normalized 18-bit weight.

5. A systolic circuit comprising:

a systolic array comprising processing elements arranged into a plurality of rows; and

a first normalizer comprising a first denormal detector, the first normalizer configured to:

receive a first input represented in floating-point with a first bit-length;

detect by the first denormal detector, that the first input is denormal based at least in part on: a value of an exponent of the first input or a value of a significand of the first input; and

generate a first normalized number represented in floating-point with a second bit-length, wherein the second bit-length is greater than the first bit-length;

wherein individual processing elements in at least one row of the systolic array are configured to:

multiply the first normalized number by a second respective normalized number to generate a multiplier product; and

add a respective input partial sum with the multiplier product to generate a respective addition result.

6. The systolic circuit of claim 5 , wherein individual processing elements in the plurality of rows of the systolic array comprise:

a multiplier configured to multiply two 18-bit floating-point numbers, wherein the multiplier is comprised of a 1-bit sign data path, a 10-bit significand data path, and a 10-bit exponent data path; and

an adder configured to add two floating-point numbers, wherein the adder is comprised of a 1-bit sign data path, a 23-bit significand data path, and an 10-bit exponent data path.

7. The systolic circuit of claim 5 , wherein the first normalizer is further configured to:

receive an input data element and a weight;

generate a normalized input data element and a normalized weight; and

select a normalized input data element or a normalized weight to be produced.

8. The systolic circuit of claim 5 , wherein the first normalizer further comprises:

a first exponent expander configured to expand a numerical range of the exponent of the first input; and

a first shifter configured to shift the significand of the first input.

9. The systolic circuit of claim 5 , wherein the first normalizer comprises:

a first leading zero encoder or counter configured to detect a number of leading zeros in the significand of the first input; and

a first shifter configured to shift the significand of the first input based at least in part on the number of leading zeros in the significand of the first input.

10. The systolic circuit of claim 5 , wherein the first normalizer is further configured to receive the first input and to expand the exponent of the first input by expanding the exponent of the first input with two extra bits.

11. The systolic circuit of claim 5 , wherein individual processing elements in the plurality of rows of the systolic array further comprise:

a multiplier;

an adder; and

wherein the multiplier and adder lack support for inputs provided in denormal form.

12. The systolic circuit of claim 5 , wherein:

the first normalizer is further configured to convert a first input into a first normalized number, wherein the first normalizer is configured to support 16-bit floating-point numbers and 16-bit brain floating-point numbers; and

wherein individual processing elements in the plurality of rows of the systolic array further comprise:

an 18-bit multiplier; and

a 34-bit adder.

13. The systolic circuit of claim 5 , wherein:

the first normalizer is further configured to convert a first input into a first normalized number, wherein the first normalizer is configured to support at least n-bit floating-point numbers, wherein n can be any number; and

wherein individual processing elements in the plurality of rows of the systolic array further comprise:

a multiplier configured to multiply at least two n-bit numbers; and

an adder configured to add two m-bit numbers, wherein m is greater than n.

14. The systolic circuit of claim 5 , further comprising:

a second normalizer configured to convert a second input into a second normalized number, the second normalizer comprising:

a second denormal detector configured to detect whether the second input is in a denormal form;

a second shifter configured to shift a significand of the second input based at least in part on the second denormal detector detecting the denormal form;

a second exponent expander configured to increase a quantity of bits representing an exponent of the second input; and

a second subtractor configured to adjust a value of the exponent of the second input to compensate for a shift of the significand of the second input.

15. The systolic circuit of claim 5 , wherein individual processing elements in the plurality of rows of the systolic array further comprise:

a multiplier;

an adder; and

wherein the adder and the multiplier are integrated together to perform a single step multiply add operation, wherein the single step multiply add operation involves a single rounding.

16. A method for systolic processing by a processing element in a systolic array of processing elements, the method comprising:

receiving, by a normalizer of the processing element, a first input represented in floating-point with a first bit-length;

detecting by a first denormal detector of the normalizer, that the first input is denormal based at least in part on: a value of an exponent of the first input or a value of a significand of the first input;

generating, by the normalizer, a first normalized number represented in floating-point with a second bit-length, wherein the second bit-length may be any bit-length that is greater than the first bit-length;

multiplying, by the processing element, the first normalized number by a second normalized number to generate a multiplier product; and

adding, by the processing element, an input partial sum with the multiplier product to generate an addition result.

17. The method of claim 16 , wherein the multiplying is performed using a multiplier that lacks support for inputs provided in denormal form.

18. The method of claim 16 , further comprising:

receiving the first input, wherein the first input may be a 16-bit floating-point number or a 16-bit brain floating-point number,

wherein the addition result is a 34-bit floating-point number.

19. The method of claim 16 , further comprising:

receiving the first input, wherein the first input may be an n-bit floating-point number where n may be any number,

wherein the addition result is an m-bit floating-point number, and wherein m is greater than n.

20. The method of claim 16 , further comprising:

receiving a third input represented in floating-point with a third bit-length;

generating a third normalized number represented in floating-point with a fourth bit-length, wherein the fourth bit-length is greater than the third bit-length; and

selecting the third normalized number or the first normalized number to be produced.