Configurable integrated circuits

1. An integrated circuit:

first and second word-line decoder circuitry;

two or more memory instances coupled to the first and second word-line decoder circuitry; and

a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances, wherein a pin bus enabled in the control block circuitry is configured to at least partially control selection of one or more of the two or more memory instances.

2. The integrated circuit of claim 1 , further comprising:

two or more input/output circuits respectively coupled to the two or more memory instances, wherein each of the two or more input/output circuits comprise a write driver, a sense amplifier, a pre-charge circuit, a multiplexer, and input and output latches.

3. The integrated circuit of claim 1 , wherein the two or more memory instances include first and second memory instances, and wherein the first word-line decoder blocks is coupled to the first and second memory instances, and wherein the pin bus comprises a two-pin bus.

4. The integrated circuit of claim 1 , wherein the two or more memory instances include first, second, third, and fourth memory instances, and wherein the first word-line decoder circuitry is coupled to the first and second memory instances and the second word-line decoder circuitry is coupled to the third and fourth memory instances, and wherein the pin bus comprises a four-pin bus.

5. The integrated circuit of claim 4 , further comprising:

respective input/output ports respectively coupled to each of the first, second, third, and fourth instances, and wherein each of the respective input/output circuits comprise a write driver, a sense amplifier, a pre-charge circuit, a multiplexer, and input and output latches.

6. The integrated circuit of claim 1 , wherein each of the two or more memory instances is coupled and configured to be at least partially controlled by a common address bus.

7. The integrated circuit of claim 6 , wherein the common address bus comprises identical address pins corresponding to identical address-bits or nearly identical address pins corresponding to at least one different address-bit, wherein the nearly identical address pins comprise at least one pin coupled to a first memory instance of the two or more memory instances and at least one pin coupled to a second memory instance of the two or more memory instances.

8. The integrated circuit of claim 1 , wherein each of the two or more memory instances is coupled to and configured to be at least partially controlled by first and second address buses.

9. The integrated circuit of claim 8 , wherein a programmable pin enabled in the control block circuitry is configured to partially control at least one of read or write operations of the two or more memory instances.

10. The integrated circuit of claim 8 ,

wherein the two or more memory instances include first, second, third, and fourth memory instances, wherein the first word-line decoder circuitry is coupled to the first and second memory instances and the second word-line decoder circuitry is coupled to the third and fourth memory instances,

wherein the first address bus is configured to at least partially control the first and second memory instances, and wherein the second address bus is configured to control the third and fourth memory instances.

11. The integrated circuit of claim 10 , wherein the first and second memory instances correspond to a first port, and wherein the third and fourth memory instances correspond to a second port.

12. The integrated circuit of claim 11 , wherein the first port corresponds to a read port, and wherein the second port corresponds to a read/write port.

13. The integrated circuit of claim 10 , wherein the first address bus is configured to at least partially control read access of the first and second memory instances, and wherein the second address bus is configured to at least partially control read access of the third and fourth memory instances.

14. The integrated circuit of claim 10 , wherein the second address bus is configured to at least partially control write access to each of the first, second, third, and fourth memory instances.

15. The integrated circuit of claim 1 , wherein the control block circuitry comprises internal clock generation circuitry.

16. The integrated circuit of claim 1 , wherein each of the first and second word-line decoder circuitry comprises word-line post decoder and driver circuitry.

17. An integrated circuit comprising:

first and second word-line decoder circuitry;

two or more memory instances coupled to the first and second word-line decoder circuitry;

a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances, wherein a programmable pin enabled in the control block circuitry is configured to partially control at least one of read or write operations of the two or more memory instances.

18. A system on chip comprising:

first and second word-line decoder circuitry;

two or more memory instances coupled to the first and second word-line decoder circuitry; and

a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances, wherein a pin bus is configured to at least partially control selection of one or more of the two or more memory instances.

19. The integrated circuit of claim 18 , wherein each of the two or more memory instances is coupled to and configured to be at least partially controlled by first and second address buses.

20. The integrated circuit of claim 19 , wherein a programmable pin is configured to partially control at least one of read or write operations of the two or more memory instances.