Pulsed level shift and inverter circuits for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
1. A level shift circuit, comprising:
an inverter circuit, comprising:
a first input terminal,
an intermediate node,
a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the intermediate node, and a source coupled to a first reference voltage, and
a first pull up device coupled between the drain of the first GaN-based transistor and a first power supply; and
a buffer circuit, comprising:
a first output terminal,
a second GaN-based transistor having a gate coupled to the intermediate node, a drain coupled to a second power supply, and a source coupled to the first output terminal, and
a first pull down device coupled between the first output terminal and a second reference voltage;
wherein the gate of the second GaN-based transistor is coupled to the intermediate node by one or more additional GaN-based transistors; and
wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the first power supply.
2. The level shift circuit of claim 1 , wherein the first power supply is a floating power supply.
3. The level shift circuit of claim 1 , wherein the voltage of the first reference voltage is substantially fixed.
4. The level shift circuit of claim 1 , wherein the voltage of the second reference voltage is configured to change in response to a signal at the first input terminal.
5. The level shift circuit of claim 1 , wherein the second power supply is a floating power supply.
6. The level shift circuit of claim 1 , wherein the first pull down device comprises a resistor.
7. The level shift circuit of claim 1 , wherein at least one of the one or more additional GaN-based transistors comprises a source coupled to a second pull down device, and wherein the second pull down device is coupled to the second reference voltage.
8. The level shift circuit of claim 1 , wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the second power supply.
9. The level shift circuit of claim 1 , wherein the gate of the second GaN-based transistor is coupled to the intermediate node by a resistor.
10. The level shift circuit of claim 1 , wherein the gate of the second GaN-based transistor is coupled to the drain of the second GaN-based transistor by one or more diodes.
11. A method of generating a level shifted signal, the method comprising:
with an inverter circuit comprising:
a first input terminal,
an intermediate node,
a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the intermediate node, and a source coupled to a first reference voltage, and
a first pull up device coupled between the drain of the first GaN-based transistor and a first power supply,
receiving an input signal at the first input terminal; and
with a buffer circuit, comprising:
a first output terminal,
a second GaN-based transistor having a gate coupled to the intermediate node, a drain coupled to a second power supply, and a source coupled to the first output terminal, and
a first pull down device coupled between the first output terminal and a second reference voltage,
generating the level shifted signal at the first output terminal based on the input signal,
wherein the voltage of the second reference voltage is configured to change in response to a signal at the first input terminal.
12. The method of claim 11 , wherein the first power supply is a floating power supply.
13. The method of claim 11 , wherein the gate of the second GaN-based transistor is coupled to the intermediate node by one or more additional GaN-based transistors.
14. The method of claim 13 , wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the first power supply.
15. The method of claim 13 , wherein at least one of the one or more additional GaN-based transistors comprises a source coupled to a second pull down device, and wherein the second pull down device is coupled to the second reference voltage.
16. The method of claim 13 , wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the second power supply.
17. The method of claim 11 , wherein the gate of the second GaN-based transistor is coupled to the intermediate node by a resistor.
18. A level shift circuit, comprising:
an inverter circuit, comprising:
a first input terminal,
an intermediate node,
a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the intermediate node, and a source coupled to a first reference voltage, and
a first pull up device coupled between the drain of the first GaN-based transistor and a first power supply; and
a buffer circuit, comprising:
a first output terminal,
a second GaN-based transistor having a gate coupled to the intermediate node, a drain coupled to a second power supply, and a source coupled to the first output terminal, and
a first pull down device coupled between the first output terminal and a second reference voltage;
wherein the gate of the second GaN-based transistor is coupled to the intermediate node by one or more additional GaN-based transistors, and
wherein at least one of the one or more additional GaN-based transistors comprises a source coupled to a second pull down device, and wherein the second pull down device is coupled to the second reference voltage.
19. The level shift circuit of claim 18 , wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the first power supply.
20. The level shift circuit of claim 18 , wherein the first power supply is a floating power supply.