IP Library Granted Patent US 11,417,685
Granted Patent B2
US 11,417,685 · App. 16/699,474 · Granted Aug 16, 2022

Fin transistor structure and fabrication method thereof

Inventors: Sheng-Yao Huang (Kaohsiung, TW); Yu-Ruei Chen (New Taipei, TW); Chung-Liang Chu (Kaohsiung, TW); Zen-Jay Tsai (Tainan, TW); Yu-Hsiang Lin (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L27/1211H01L21/823431H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,417,685
App. No.
16/699,474
Granted
Aug 16, 2022
Kind
B2
Abstract

A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

Claims (14)

1. A fin transistor structure, comprising:

a first substrate;

an insulation layer, disposed on the first substrate;

a plurality of fin structures, disposed on the insulation layer;

a supporting dielectric layer, fixing the fin structures at waist parts of the fin structures; and

a gate structure layer, disposed on the supporting dielectric layer and covering a portion of the fin structures,

wherein a part of each of the fin structures between the insulation layer and the supporting dielectric layer is exposed by an air space.

2. The fin transistor structure according to claim 1 , wherein the fin structures are a portion of a second substrate, and the second substrate is disposed on the insulation layer on the first substrate.

3. The fin transistor structure according to claim 2 , wherein the second substrate further has a bulk part surrounding the fin structures and an end part of the supporting dielectric layer is fixed to the bulk part of the second substrate.

4. The fin transistor structure according to claim 3 , wherein the insulation layer covers an end surface of the bulk part so as to be attached to the first substrate.

5. The fin transistor structure according to claim 1 , wherein the insulation layer covers a portion of side walls of the fin structures lower than the waist parts.

6. The fin transistor structure according to claim 1 , wherein each of the fin structures has a first end surface on the insulation layer and a second end surface opposite to the first end surface and covered by the gate structure layer, wherein the second end surface is wider than the first end surface along a cross-sectional direction with respect to the fin structures.

7. The fin transistor structure according to claim 1 , wherein a distance from the first substrate to the waist part of each of the fin structures is equal to or more than a half of a height of each of the fin structures.

8. The fin transistor structure according to claim 1 , wherein the insulation layer is an oxide layer, a nitride layer or a dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2019
From: HUANG, SHENG-YAO; CHEN, YU-RUEI; CHU, CHUNG-LIANG; TSAI, ZEN-JAY; LIN, YU-HSIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 051138/0616 →
Priority Claims (1)
CN 201910948784.3 · Oct 8, 2019 · national
Continuity (1)
Related Publication 20210104554A1 · Apr 8, 2021
Cited By (1)
US 12,500,183