Field-effect transistors with dual thickness gate dielectrics
Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.
1. A transistor arrangement, comprising:
a semiconductor material;
a source region and a drain region in the semiconductor material; and
a gate stack over a portion of the semiconductor material that is between the source region and the drain region, wherein the portion includes a first portion and a second portion, and the gate stack includes:
one or more gate electrode materials,
a first gate dielectric between the first portion of the semiconductor material and the one or more gate electrode materials, and
a second gate dielectric between the second portion of the semiconductor material and the one or more gate electrode materials,
wherein a thickness of the first gate dielectric is different from a thickness of the second gate dielectric, and wherein a dielectric constant of the first gate dielectric is different from a dielectric constant of the second gate dielectric.
2. The transistor arrangement according to claim 1 , wherein:
the first portion of the semiconductor material is closer to the source region than the second portion of the semiconductor material, and
the second portion of the semiconductor material is closer to the drain region than the first portion of the semiconductor material.
3. The transistor arrangement according to claim 2 , wherein a distance between the second portion of the semiconductor material and the drain region is between 10 and 1000 nanometers.
4. The transistor arrangement according to claim 2 , wherein the thickness of the second gate dielectric is larger than the thickness of the first gate dielectric and wherein the dielectric constant of the second gate dielectric is smaller than the dielectric constant of the first gate dielectric.
5. The transistor arrangement according to claim 1 , wherein the thickness of the second gate dielectric is larger than the thickness of the first gate dielectric and wherein the dielectric constant of the second gate dielectric is at least 3 times smaller than the dielectric constant of the first gate dielectric.
6. The transistor arrangement according to claim 1 , wherein:
the first portion of the semiconductor material includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
the second portion of the semiconductor material includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter.
7. The transistor arrangement according to claim 1 , wherein:
each of the first portion and the second portion of the semiconductor material includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
a portion of the semiconductor material that is between the second portion and the drain region includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter.
8. The transistor arrangement according to claim 1 , wherein:
the first portion of the semiconductor material portion includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter,
a portion of the second portion of the semiconductor material that is closest to the first portion includes dopants of the first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
a portion of the second portion of the semiconductor material that is between the portion of the second portion of the semiconductor material that is closest to the first portion and the drain region includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter.
9. The transistor arrangement according to claim 1 , wherein:
a portion of the first portion of the semiconductor material that is closest to the source region includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter,
a portion of the first portion of the semiconductor material that is between the portion of the first portion of the semiconductor material that is closest to the source region and the second portion of the semiconductor material includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
the second portion of the semiconductor material includes dopants of the second type.
10. The transistor arrangement according to claim 9 , wherein:
each of the source region and the drain region includes dopants of the second type, and
dopant concentration of the dopants of the second type in each of the source region and the drain region is at least 1×10 21 dopant atoms per cubic centimeter.
11. The transistor arrangement according to claim 1 , wherein:
the one or more gate electrode materials over the first gate dielectric include a work function (WF) material and a gate electrode material so that the WF material is between the gate electrode material and the first gate dielectric, and
the one or more gate electrode materials over the first gate dielectric include the gate electrode material in contact with the second gate dielectric.
12. The transistor arrangement according to claim 1 , wherein:
each of the source region and the gate stack is coupled to a ground potential, and
the drain region is coupled to each of an input/output port and a further circuit.
13. The transistor arrangement according to claim 12 , wherein the further circuit is a receiver circuit.
14. The transistor arrangement according to claim 1 , wherein:
at least a portion of the first portion includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
at least a portion of the second portion or a portion of the semiconductor material that is between the second portion and the drain region includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter.
15. An electronic device, comprising:
an input/output (I/O) port;
a receiver circuit, having an input coupled to the I/O port;
an electrostatic discharge protection (ESD) circuit, coupled to the I/O port and to the input of the receiver circuit; and
a diode,
wherein:
the ESD circuit includes a transistor having a source region, a drain region, and a gate stack,
each of the source region and the gate stack is coupled to a ground potential,
the ESD circuit is coupled to the I/O port and to the input of the receiver circuit by having the drain region coupled to the I/O port and to the input of the receiver circuit, and
the diode is coupled between the ground potential and the I/O port.
16. The electronic device according to claim 15 , wherein:
the electronic device further includes a silicon controlled rectifier (SCR) circuit,
the drain region is coupled to the I/O port and to the input of the receiver circuit by being coupled to the SCR circuit and the SCR circuit being coupled to the I/O port and to the input of the receiver circuit.
17. The electronic device according to claim 15 , wherein the transistor is an extended drain transistor.
18. The electronic device according to claim 15 , wherein:
a first portion of the gate stack that includes a first gate dielectric,
a second portion of the gate stack includes a second gate dielectric,
a thickness of the first gate dielectric is smaller than a thickness of the second gate dielectric, and
the first portion of the gate stack is closer to the source region than the second portion of the gate stack.
19. A method of forming a transistor arrangement, the method comprising:
providing a source region and a drain region in a semiconductor material; and
providing a gate stack over a portion of the semiconductor material that is between the source region and the drain region, wherein the portion includes a first portion and a second portion, and the gate stack includes:
one or more gate electrode materials,
a first gate dielectric between the first portion of the semiconductor material and the one or more gate electrode materials, and
a second gate dielectric between the second portion of the semiconductor material and the one or more gate electrode materials,
wherein:
a thickness of the first gate dielectric is different from a thickness of the second gate dielectric,
at least a portion of the first portion includes dopants of a first type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter, and
at least a portion of the second portion or a portion of the semiconductor material that is between the second portion and the drain region includes dopants of a second type at a dopant concentration between 1×10 16 and 1×10 18 dopant atoms per cubic centimeter.
20. The method according to claim 19 , wherein:
the first portion of the semiconductor material is closer to the source region than the second portion of the semiconductor material,
the second portion of the semiconductor material is closer to the drain region than the first portion of the semiconductor material, and
the thickness of the second gate dielectric is larger than the thickness of the first gate dielectric.