Integrated circuit devices

1. An integrated circuit device comprising:

a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction;

at least one semiconductor layer, each comprising a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and

a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions,

wherein the lower semiconductor layer comprises a same material as a material of the upper semiconductor layer,

wherein a semiconductor interface is provided between a top surface of the lower semiconductor layer and a lowest surface of the upper semiconductor layer,

wherein at least a portion of the semiconductor interface extends from a first end of the semiconductor interface to an interior of the semiconductor interface along a plane parallel to a top surface of the substrate and at least another portion of the semiconductor interface has a slope with respect to the top surface of the substrate and extends from the interior of the semiconductor interface to a second end of the semiconductor interface opposite the first end, and

wherein the lower semiconductor layer and the upper semiconductor layer have a same crystallinity.

2. The integrated circuit device of claim 1 , further comprising:

at least one source/drain region on the at least one semiconductor layer and the at least one of the plurality of fin-type active regions.

3. The integrated circuit device of claim 1 , further comprising:

a nano-sheet stacked structure comprising a plurality of nano-sheets stacked apart from one another above a top surface of a fin-type active region, among the plurality of the fin-type active regions, and extending parallel to the top surface of the fin-type active region, each of the plurality of nano-sheets comprising a channel region,

wherein portions of a gate electrode, among the plurality of gate electrodes, fill spaces between the nano-sheets.

4. The integrated circuit device of claim 3 , wherein a topmost level of the semiconductor interface relative to the substrate in a vertical direction is higher than a level of a bottom surface of a nano-sheet, among the plurality of nano-sheets, closest to the substrate.

5. The integrated circuit device of claim 4 , wherein the topmost level of the semiconductor interface relative to the substrate in the vertical direction is lower than a level of a top surface of the nano-sheet closest to the substrate.

6. The integrated circuit device of claim 1 , wherein:

the at least one semiconductor layer comprises at least three semiconductor layers respectively arranged on at least three fin-type active regions arranged in the second horizontal direction at a constant pitch from among the plurality of fin-type active regions;

at least a portion of a semiconductor interface of at least one outer semiconductor layer, from among the at least three semiconductor layers, has a slope with respect to the top surface of the substrate; and

a semiconductor interface of at least one inner semiconductor layer, from among the at least three semiconductor layers, is along a plane parallel to the top surface of the substrate.

7. The integrated circuit device of claim 6 , wherein the semiconductor interface of the at least one outer semiconductor layer from among the at least three semiconductor layers has a first portion parallel to the top surface of the substrate and at least one second portion having a slope with respect to the top surface of the substrate.

8. An integrated circuit device comprising:

a plurality of first fin-type active regions extending from a top surface of a substrate, in a first peripheral circuit region, in a first horizontal direction;

a plurality of second fin-type active regions extending from the top surface of the substrate, in a second peripheral circuit region, in the first horizontal direction;

a plurality of first semiconductor layers on the plurality of first fin-type active regions and each comprising:

a first lower semiconductor layer and a first upper semiconductor layer sequentially stacked on a corresponding first fin-type active region among the plurality of first fin-type active regions, and

a first semiconductor interface between a top surface of the first lower semiconductor layer and a lowest surface of the first upper semiconductor layer;

a plurality of second semiconductor layers on the plurality of second fin-type active regions and each comprising:

a second lower semiconductor layer and a second upper semiconductor layer sequentially stacked on a corresponding second fin-type active region among the plurality of second fin-type active regions, and

a second semiconductor interface between the second lower semiconductor layer and the second upper semiconductor layer; and

a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the substrate,

wherein a topmost level of the first semiconductor interface relative to the substrate in the vertical direction is higher than a topmost level of the second semiconductor interface relative to the substrate in the vertical direction, and

a first semiconductor interface of at least one outer first semiconductor layer from among the plurality of first semiconductor layers has a slope, extending from end to end of the first semiconductor interface, with respect to the top surface of the substrate.

9. The integrated circuit device of claim 8 , wherein, in the second horizontal direction, a first width of the first peripheral circuit region is less than a second width of the second peripheral circuit region.

10. The integrated circuit device of claim 8 , wherein, in the second horizontal direction, a third width of each of the plurality of first semiconductor layers is less than a fourth width of each of the plurality of second semiconductor layers.

11. The integrated circuit device of claim 8 , wherein a level of a top surface of each of the plurality of first semiconductor layers is higher than a level of a top surface of each of the plurality of second semiconductor layers.

12. The integrated circuit device of claim 8 , wherein:

a first semiconductor interface of at least one inner first semiconductor layer from among the plurality of first semiconductor layers is along a plane parallel to the top surface of the substrate.

13. The integrated circuit device of claim 8 , wherein:

a second semiconductor interface of at least one outer second semiconductor layer from among the plurality of second semiconductor layers comprises a portion parallel to the top surface of the substrate and at least one other portion having a slope with respect to the top surface of the substrate; and

a second semiconductor interface of at least one inner second semiconductor layer from among the plurality of second semiconductor layers is along a plane parallel to the top surface of the substrate.

14. An integrated circuit device comprising:

a plurality of fin-type active regions protruding from a top surface of a substrate, which includes a cell region and a peripheral circuit region, and extending in a first horizontal direction;

a nano-sheet stacked structure comprising a plurality of nano-sheets stacked apart from one another above a top surface of a fin-type active region in the cell region, among the plurality of the fin-type active regions, and extending parallel to the top surface of the fin-type active region, each of the plurality of nano-sheets comprising a channel region;

at least one semiconductor layer each comprising:

a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions, and

a semiconductor interface between the lower semiconductor layer and the upper semiconductor layer; and

a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions,

wherein, in the peripheral circuit region, the lower semiconductor layer and the upper semiconductor layer have a same crystallinity, and

wherein at least a portion of the semiconductor interface extends from a first end of the semiconductor interface to an interior of the semiconductor interface along a plane parallel to a top surface of the substrate and at least another portion of the semiconductor interface has a slope with respect to the top surface of the substrate and extends from the interior of the semiconductor interface to a second end of the semiconductor interface opposite the first end.

15. The integrated circuit device of claim 14 , wherein a topmost level of the semiconductor interface relative to the substrate in a vertical direction is lower than a level of a top surface of a nano-sheet, among the plurality of nano-sheets, closest to the substrate.

16. The integrated circuit device of claim 14 , wherein, in the peripheral circuit region, a fin-type active region, among the plurality of fin-type active regions, the lower semiconductor layer, and the upper semiconductor layer have the same crystallinity.