Memory system and method for controlling nonvolatile memory
According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks; and
a controller electrically connected to the nonvolatile memory and configured to:
manage, per physical address in which data have been stored, the number of logical addresses associated with the physical address; and
perform garbage collection by:
copying first data from a first physical address in a copy-source block to a first block and not copying second data from a second physical address in the copy-source block to the first block; and
copying the second data from the second physical address in the copy-source block to a second block and not copying the first data from the first physical address in the copy-source block to the second block, wherein
the number of logical addresses associated with the first physical address belongs to a first range,
the number of logical addresses associated with the second physical address belongs to a second range different from the first range.
2. The memory system of claim 1 , wherein,
when the first data is data having a lifetime longer than a lifetime of the second data, the first range is greater than the second range.
3. The memory system of claim 1 , wherein
the controller is further configured to:
when write data received from a host is update data of data already stored in the nonvolatile memory, decrement the number of logical addresses associated with a physical address of the data by one.
4. The memory system of claim 1 , wherein
the controller is further configured to:
in response to receiving write data from a host,
in a case where third data that matches with the write data is not stored in the nonvolatile memory,
write the write data to the nonvolatile memory,
update a first translation table managing a corresponding relationship between logical addresses and intermediate addresses to associate first intermediate address with a logical address of the write data,
update a second translation table managing a corresponding relationship between the intermediate addresses and physical addresses to associate a third physical address with the first intermediate address, the third physical address indicating a location of the nonvolatile memory in which the write data is written, and
set the number of logical addresses associated with the third physical address to one; and
in a case where the third data that matches with the write data is already stored in the nonvolatile memory,
without writing the write data to the nonvolatile memory, update the first translation table to associate a second intermediate address with the logical address of the write data, the second intermediate address being associated with a fourth physical address in the second translation table, the fourth physical address indicating a location of the nonvolatile memory in which the third data is stored, and
increment the number of logical addresses associated with the fourth physical address by one.
5. A memory system comprising:
a nonvolatile memory including a plurality of blocks; and
a controller electrically connected to the nonvolatile memory and configured to:
manage, per physical address in which data have been stored, the number of logical addresses associated with the physical address; and
perform garbage collection by selecting first data in preference to second data as copy target data for the garbage collection, wherein
the first data is stored at a first physical address,
the number of logical addresses associated with the first physical address belongs to a first range,
the second data is stored at a second physical address,
the number of logical addresses associated with the second physical address belongs to a second range, and
the first range is greater than the second range.
6. The memory system of claim 5 , wherein
the first data is data having a lifetime longer than a lifetime of the second data.
7. The memory system of claim 5 , wherein
the controller is further configured to:
when write data received from a host is update data of data already stored in the nonvolatile memory, decrement the number of logical addresses associated with a physical address of the data by one.
8. The memory system of claim 5 , wherein
the controller is further configured to:
in response to receiving write data from a host,
in a case where third data that matches with the write data is not stored in the nonvolatile memory,
write the write data to the nonvolatile memory,
update a first translation table managing a corresponding relationship between logical addresses and intermediate addresses to associate first intermediate address with a logical address of the write data,
update a second translation table managing a corresponding relationship between the intermediate addresses and physical addresses to associate a third physical address with the first intermediate address, the third physical address indicating a location of the nonvolatile memory in which the write data is written, and
set the number of logical addresses associated with the third physical address to one; and
in a case where the third data that matches with the write data is already stored in the nonvolatile memory,
without writing the write data to the nonvolatile memory, update the first translation table to associate a second intermediate address with the logical address of the write data, the second intermediate address being associated with a fourth physical address in the second translation table, the fourth physical address indicating a location of the nonvolatile memory in which the third data is stored, and
increment the number of logical addresses associated with the fourth physical address by one.
9. A memory system comprising:
a nonvolatile memory including a plurality of blocks; and
a controller electrically connected to the nonvolatile memory and configured to:
manage, per physical address in which data have been stored, the number of logical addresses associated with the physical address; and
when executing garbage collection, copy data stored at a copy-source physical address of the nonvolatile memory to a copy-destination physical address of the nonvolatile memory, and associate the number of logical addresses that has been associated with the copy-source physical address with the copy-destination physical address.
10. The memory system of claim 9 , wherein
the controller is further configured to:
when write data received from a host is update data of data already stored in the nonvolatile memory, decrement the number of logical addresses associated with a physical address of the data by one.
11. The memory system of claim 9 , wherein
the controller is further configured to:
in response to receiving write data from a host,
in a case where third data that matches with the write data is not stored in the nonvolatile memory,
write the write data to the nonvolatile memory,
update a first translation table managing a corresponding relationship between logical addresses and intermediate addresses to associate first intermediate address with a logical address of the write data,
update a second translation table managing a corresponding relationship between the intermediate addresses and physical addresses to associate a third physical address with the first intermediate address, the third physical address indicating a location of the nonvolatile memory in which the write data is written, and
set the number of logical addresses associated with the third physical address to one; and
in a case where the third data that matches with the write data is already stored in the nonvolatile memory,
without writing the write data to the nonvolatile memory, update the first translation table to associate a second intermediate address with the logical address of the write data, the second intermediate address being associated with a fourth physical address in the second translation table, the fourth physical address indicating a location of the nonvolatile memory in which the third data is stored, and increment the number of logical addresses associated with the fourth physical address by one.