NAND string utilizing floating body memory cell

1. A NAND string configuration comprising:

a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;

a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; and

a select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;

wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;

wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;

wherein said third region is commonly connected to at least two of said semiconductor memory cells;

wherein each of said at least one of said plurality of semiconductor memory cells has only one gate; and

wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.

2. The NAND string configuration of claim 1 , wherein all serial connections between said semiconductor memory cells are not connected to any terminals, so that only said select gate drain device and said select gate source device are connected to terminals.

3. The NAND string configuration of claim 1 , said NAND string being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one semiconductor memory cell.

4. The NAND string configuration of claim 3 , wherein at least one of said plurality of semiconductor memory cells each comprise a back bias region configured to perform said at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.

5. The NAND string configuration of claim 4 , wherein said floating body region is provided in a fin structure that extends vertically above said back bias region.

6. The NAND string configuration of claim 4 , wherein a constant voltage bias is applied to said back bias region.

7. The NAND string configuration of claim 4 , wherein a periodic pulse of voltage is applied to said back bias region.

8. A semiconductor memory array comprising:

a plurality of NAND string configurations, each said NAND string configuration comprising:

a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;

a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and

a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;

wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a third region in electrical contact with said floating body region and spaced apart from said first and second regions;

wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;

wherein said third region is commonly connected to at least two of said semiconductor memory cells;

wherein each said at least one of said plurality of semiconductor memory cells has only one gate;

wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals; and

wherein said semiconductor memory array comprises at least one of: at least two of said select gate drain devices connected to a common bit line; or at least two of said select gate source devices connected to a common source line.

9. The semiconductor memory array of claim 8 , wherein said semiconductor array comprises:

a first set of two or more NAND string configurations connected to said common bit line, wherein said common bit line is a first common bit line; and

at least a second set of two or more NAND string configurations connected to at least a second common bit line;

wherein said first common bit line and said at least a second common bit line are connected to a primary bit line.

10. The semiconductor memory array of claim 8 , wherein said semiconductor array comprises:

a first set of two or more NAND string configurations connected to said common source line, wherein said common source line is a first common source line; and

at least a second set of two or more NAND string configurations connected to at least a second common source line;

wherein said first common source line and said at least a second common source line are connected to a primary source line.

11. The semiconductor memory array of claim 8 , wherein at least one of said semiconductor memory cells each comprise a back-bias region configured to perform at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.

12. The semiconductor memory array of claim 11 , wherein said floating body region is provided in a fin structure that extends vertically above said back bias region.

13. The semiconductor memory array of claim 11 , wherein a constant voltage bias is applied to said back bias region.

14. The semiconductor memory array of claim 11 , wherein a periodic pulse of voltage is applied to said back bias region.