IP Library Granted Patent US 10,923,488
Granted Patent B2
US 10,923,488 · App. 16/707,960 · Granted Feb 16, 2021

Semiconductor device

Inventor: Wataru Sakamoto (Yokkaichi, JP)
Assignee: Toshiba Memory Corporation
H01L27/11556H01L27/1157H01L27/11519H01L27/11524H01L27/11565H01L27/11582H01L29/1037H01L29/40114H01L29/40117
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Quick Facts
Patent No.
US 10,923,488
App. No.
16/707,960
Granted
Feb 16, 2021
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

Claims (38)

1. A semiconductor device comprising:

a substrate;

a first stacked body disposed above the substrate, the first stacked body including a first electrode layer and a second electrode layer, the second electrode layer being disposed above the first electrode layer;

a first semiconductor layer extending in a first direction in the first stacked body;

a first charge storage portion provided between the first semiconductor layer and the first electrode layer;

a second charge storage portion provided between the first semiconductor layer and the second electrode layer;

a second stacked body disposed on the first stacked body, the second stacked body including a third electrode layer and a fourth electrode layer, the fourth electrode layer being disposed above the third electrode layer;

a second semiconductor layer extending in the first direction in the second stacked body, a bottom end of the second semiconductor layer connecting a top end of the first semiconductor layer;

a third charge storage portion provided between the second semiconductor layer and the third electrode layer; and

a fourth charge storage portion provided between the second semiconductor layer and the fourth electrode layer,

a first diameter of a first portion of the first semiconductor layer being smaller than a second diameter of a second portion of the first semiconductor layer, the first portion being surrounded by the first charge storage portion, and the second portion being surrounded by the second charge storage portion,

a third diameter of a third portion of the second semiconductor layer being smaller than a fourth diameter of a fourth portion of the second semiconductor layer, the third portion being surrounded by the third charge storage portion, and the fourth portion being surrounded by the fourth charge storage portion,

the second diameter being larger than the third diameter,

a first thickness of the first charge storage portion between the first semiconductor layer and the first electrode layer being thinner than a second thickness of the second charge storage portion between the first semiconductor layer and the second electrode layer, and

a third thickness of the third charge storage portion between the second semiconductor layer and the third electrode layer being thinner than a fourth thickness of the fourth charge storage portion between the second semiconductor layer and the fourth electrode layer.

2. The device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are cylindrical.

3. The device according to claim 2 , wherein the first thickness, the second thickness, the third thickness, and the fourth thickness are thicknesses along a radial direction of the first semiconductor layer.

4. The device according to claim 1 , further comprising:

a first core portion of insulation, the first core portion being surrounded by the first semiconductor layer; and

a second core portion of insulation, the second core portion being surrounded by the second semiconductor layer.

5. The device according to claim 4 , wherein,

the second core portion contacts the first core portion,

the first core portion includes a first side surface and a stepped surface, the first side surface contacting the first semiconductor layer,

the second core portion includes a second side surface, the second side surface contacting the second semiconductor layer, and

the stepped surface is disposed between the first side surface and the second side surface.

6. The device according to claim 1 , wherein the substrate, the first stacked body, and the second stacked body are arranged in the first direction.

7. The device according to claim 1 , wherein the first thickness, the second thickness, the third thickness, and the fourth thickness are thicknesses along a second direction, the second direction is orthogonal to the first direction.

8. The device according to claim 1 , wherein the second thickness is thicker than the third thickness.

9. The device according to claim 1 , wherein the first charge storage portion contains silicon.

10. The device according to claim 1 , wherein the first charge storage portion contains silicon nitride.

11. The device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer function as channel bodies.

12. The device according to claim 1 , further comprising:

a source layer extending in the first direction and a second direction in the first stacked body and the second stacked body, the second direction being orthogonal to the first direction.

13. The device according to claim 12 , wherein the source layer is electrically connected to a bottom end of the first semiconductor layer.

14. The device according to claim 1 , further comprising:

a separating portion extending in the first direction and a second direction and separating both the first stacked body and the second stacked body in a third direction, the second direction and the third direction being orthogonal to the first direction, the second direction crossing to the third direction; and

a source layer extending in the first direction and the second direction in the separating portion.

15. The device according to claim 14 , wherein the source layer is electrically connected to a bottom end of the first semiconductor layer.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 057016/0551 →
MERGER Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 057016/0586 →
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057016/0611 →