Read-once memory

1. A volatile memory circuit, comprising:

a first flip-flop;

a second flip-flop having a set input coupled to an output of the first flip-flop;

first logic circuitry, which, in operation, logically combines an output of the second flip-flop, a readout control signal, and information representative of the output of the first flip-flop; and

second logic circuitry, which, in operation, logically combines the readout control signal and a cell programming control signal, wherein an input of the first flip-flop is coupled to an output of the second logic circuitry.

2. The circuit of claim 1 , wherein the second logic circuitry includes circuitry of an XOR-type.

3. The circuit of claim 1 , wherein the first logic circuitry includes logic circuitry of an AND type, and, in operation, receives an inverted output of the first flip-flop.

4. The circuit of claim 1 , wherein the output of the second logic circuitry is coupled to a reset input of the first flip-flop.

5. The circuit of claim 1 , wherein the first logic circuitry includes logic circuitry of a NAND type.

6. The circuit of claim 1 , wherein the output of the second logic circuitry is coupled to a set input of the first flip-flop.

7. The circuit of claim 1 , wherein, in operation, a reading of a state stored in the memory circuit triggers a forcing by the first logic circuitry of an output of the circuit to a constant state.

8. The circuit of claim 1 , wherein, in operation, outputting a reading of content of the first flip-flop by the circuit is preceded by an erasing of the content of the first flip-flop.

9. The circuit of claim 1 , wherein an input of the first logic circuitry is coupled to a readout control input of the circuit, which, in operation, receives the readout control signal.

10. The circuit of claim 1 , wherein the flip-flops are of RS type.

11. The circuit of claim 1 , comprising a clock input coupled to clock inputs of the first and second flip-flops.

12. A system, comprising:

one or more processing circuits; and

one or more memories coupled to the one or more processing circuits, the one or more memories including a read-once memory circuit having a plurality of memory cells, each of the plurality of memory cells of the read-once memory including:

a first flip-flop;

a second flip-flop having a set input coupled to an output of the first flip-flop;

first logic circuitry, which, in operation, logically combines an output of the second flip-flop, a readout control signal, and information representative of the output of the first flip-flop to generate an output of the read-once memory; and

second logic circuitry, which in operation, logically combines the readout control signal of the read-once memory circuit and a cell programming control signal of the read-once memory circuit, wherein an input of the first flip-flop is coupled to an output of the second logic circuitry.

13. The system of claim 12 , wherein the second logic circuitry includes an XOR gate.

14. The system of claim 12 , wherein the output of the second logic circuitry is coupled to respective reset inputs of the first flip-flops of the plurality of memory cells.

15. The system of claim 12 , wherein the output of the second logic circuitry is coupled to respective set inputs of the first flip-flops of the plurality of memory cells.

16. The system of claim 12 , wherein the first logic circuitry of a memory cell of the plurality of memory cells includes an AND gate, which, in operation, receives an inverted output of the first flip-flop of the memory cell of the plurality of memory cells.

17. The system of claim 12 , wherein the read-once memory, in operation, responds to receipt of a command to read content stored in the first flip-flops of the plurality of memory cells by:

resetting the first flip-flops of the plurality of memory cells; and

subsequently outputting content of the second flip-flops of the plurality of memory cells.

18. The system of claim 17 , wherein, in operation, the read-once memory resets the second flip-flops of the plurality of memory cells after outputting the content of the second flip-flops of the plurality of memory cells.

19. A method, comprising:

storing data in a first flip-flop of a memory cell;

transferring the data to a second flip-flop of the memory cell, the second flip-flop having a set input coupled to an output of the first flip-flop;

logically combining an output of the second flip-flop, a readout control signal, and information representative of the output of the first flip-flop to generate an output of the memory cell;

logically combining the readout control signal and a cell programming control signal, and providing a result of the logical combining to an input of the first flip-flop; and

in response to receipt of a read command,

resetting the first flip-flop; and

outputting the data.

20. The method of claim 19 , comprising resetting the second flip-flop after outputting the data.